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mixed signal isp flash mcu family c8051f300/1/2/3/4/5 rev. 2.9 12/08 copyright ? 2008 by silicon laboratories c8051f30x analog peripherals - 8-bit adc ('f300/2 only) ? up to 500 ksps ? up to 8 external inputs ? programmable amplifier gains of 4, 2, 1, & 0.5 ? vref from external pin or v dd ? built-in temperature sensor ? external conversion start input - comparator ? programmable hysteresis and response time ? configurable as interrupt or reset source ? low current ( ? 0.5 a) on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, ? inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - complete development kit supply voltage 2.7 to 3.6 v - typical operating current: 6.6 ma @ 25 mhz; 14 a @ 32 khz - typical stop mode current: 0.1 a - temperature range: ?40 to +85 c high speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler memory - 256 bytes internal data ram - up to 8 kb (?f300/1/2/3), 4 kb (?f304), or 2 kb (?f 305) flash; 512 bytes are reserved in the 8 kb dev ices digital peripherals - 8 port i/o; all 5 v tolerant with high sink current - hardware enhanced uart and smbus? serial ports - three general-purpose 16-bit counter/timers - 16-bit programmable count er array (pca) with three capture/compare modules - real time clock mode using pca or timer and ? external clock source clock sources - internal oscillator: 24.5 mhz with 2% accuracy supp orts uart operation - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - can switch between clock sources on-the-fly; useful in power saving modes 11-pin qfn or 14-pin soic package - qfn size = 3x3 mm analog peripherals pga 8/4/2 kbytes isp flash 256 b sram por debug circuitry 12 interrupts 8051 cpu (25mips) digital i/o programmable precision internal oscillator high-speed controller core a m u x i/o port crossbar uart smbus pca timer 0 timer 1 timer 2 voltage comparator + - wdt 8-bit 500 ksps adc temp sensor c8051f300/2 only
c8051f300/1/2/3/4/5 2 rev. 2.9 n otes :
rev. 2.9 3 c8051f300/1/2/3/4/5 table of contents 1. system overview............ ............................................................................. ........... 13 1.1. cip-51? microcontroller core.. ............................................................. ........... 16 1.1.1. fully 8051 compatible...... ............................................................. ........... 16 1.1.2. improved throughput ............ ........................................................ ........... 16 1.1.3. additional features .......... ............................................................. ........... 17 1.2. on-chip memory......... ........................................................................... ........... 18 1.3. on-chip debug circuitr y.................... .................................................. ............. 19 1.4. programmable digital i/o and crossbar ............... ................................. ........... 19 1.5. serial ports ............ ................................................................................ ........... 20 1.6. programmable counter array ... ............................................................. ........... 21 1.7. 8-bit analog to digital c onverter (c8051f300/2 only) ..... ............ ........... ......... 22 1.8. comparator ............... ............................................................................. ........... 23 2. absolute maximum ratings ........ ............................................................... ........... 24 3. global electrical characteristic s .................. ............................................. ........... 25 4. pinout and package definitions..... ............... ............................................. ........... 27 5. adc0 (8-bit adc, c8051f300/2).... ............................................................. ........... 35 5.1. analog multiplexer and pga..... ............................................................. ........... 36 5.2. temperature sensor ............ .................................................................. ........... 36 5.3. modes of operation ............. .................................................................. ........... 39 5.3.1. starting a conversion....... ............................................................. ........... 39 5.3.2. tracking modes................ ............................................................. ........... 40 5.3.3. settling time r equirements ................ .......................................... ........... 41 5.4. programmable window detector ........................................................... ........... 45 5.4.1. window detector in sing le-ended mode .......... ............................ ........... 45 5.4.2. window detector in differential mode..... .............. ............... ........... ......... 46 6. voltage reference (c8051f300/2) . ............................................................. ........... 49 7. comparator0 ................ ................................................................................ ........... 51 8. cip-51 microcontroller .............. .................................................................. ........... 57 8.1. instruction set ........... ............................................................................. ........... 58 8.1.1. instruction and cpu timing .. ........................................................ ........... 58 8.1.2. movx instruction and program memory ... ................................. ............. 59 8.2. memory organization........... .................................................................. ........... 63 8.2.1. program memory.............. ............................................................. ........... 63 8.2.2. data memory........ ......................................................................... ........... 64 8.2.3. general purpose registers ........................................................... ........... 64 8.2.4. bit addressable lo cations.............. ............................................... ........... 65 8.2.5. stack ................. ........................................................................... ........... 65 8.2.6. special function registers. ........................................................... ........... 65 8.2.7. register descriptions ....... ............................................................. ........... 68 8.3. interrupt handler ................ .................................................................. ............. 72 8.3.1. mcu interrupt sources a nd vectors ............ ................................. ........... 72 8.3.2. external interrupts .......... ............................................................... ........... 73 8.3.3. interrupt priorities ........ .................................................................. ........... 73
c8051f300/1/2/3/4/5 4 rev. 2.9 8.3.4. interrupt latency .............. ............................................................. ........... 73 8.3.5. interrupt register descrip tions.............. .......................................... ......... 75 8.4. power management modes ........... ........................................................ ........... 80 8.4.1. idle mode............ ........................................................................... ........... 80 8.4.2. stop mode ...................... ............................................................... ........... 81 9. reset sources.......... .................................................................................. ............. 83 9.1. power-on reset .................. .................................................................. ........... 84 9.2. power-fail reset/vdd monitor. ............................................................. ........... 84 9.3. external reset .......... ............................................................................. ........... 85 9.4. missing clock dete ctor reset................. ............................................... ........... 85 9.5. comparator0 reset..... ........................................................................... ........... 85 9.6. pca watchdog timer reset....... ........................................................... ........... 85 9.7. flash error reset...... ............................................................................. ........... 86 9.8. software reset ......... ............................................................................. ........... 86 10. flash memory ................. ............................................................................. ........... 89 10.1.programming the flash memory .......................................................... ........... 89 10.1.1.flash lock and key functi ons ................ .............. ............... ........... ......... 89 10.1.2.flash erase procedure ...... ........................................................... ........... 89 10.1.3.flash write procedure ..... ............................................................. ........... 90 10.2.non-volatile data st orage................. .................................................. ............. 90 10.3.security options ....... ............................................................................. ........... 90 10.4.flash write and erase guidelines ............... .......................................... ........... 94 10.4.1.v dd maintenance and the v dd monitor ............ ............................ ........... 94 10.4.2.pswe maintenance ......... ............................................................. ........... 94 10.4.3.system clock ....... ......................................................................... ........... 95 11. oscillators ................ .................................................................................. ............. 97 11.1.programmable internal oscilla tor .................... .............. ............... ........... ......... 97 11.2.external oscillator drive circuit................ ............................................. ........... 99 11.3.system clock selectio n......................................................................... ........... 99 11.4.external crystal example .... .................................................................. ......... 101 11.5.external rc example .......... .................................................................. ......... 102 11.6.external capacitor example ... ............................................................... ......... 102 12. port input/output............ ............................................................................. ......... 103 12.1.priority crossbar decoder ... .................................................................. ......... 104 12.2.port i/o initialization ........ ...................................................................... ......... 106 12.3.general purpose port i/o .... .................................................................. ......... 108 13. smbus ................. ......................................................................................... ......... 111 13.1.supporting documents ............. ............................................................. ......... 112 13.2.smbus configuration... ............... ........................................................... ......... 112 13.3.smbus operation ....... ........................................................................... ......... 112 13.3.1.arbitration......... ............................................................................. ......... 113 13.3.2.clock low extension........ ............................................................. ......... 114 13.3.3.scl low timeout.... ...................................................................... ......... 114 13.3.4.scl high (smbus free) ti meout .............. ................................. ........... 114
rev. 2.9 5 c8051f300/1/2/3/4/5 13.4.using the smbus........ ........................................................................... ......... 115 13.4.1.smbus configuration regist er................ .............. ............... .................. 116 13.4.2.smb0cn control register . ........................................................... ......... 119 13.4.3.data register ....... ......................................................................... ......... 122 13.5.smbus transfer modes... ...................................................................... ......... 123 13.5.1.master transmitter mode .. ............... ............................................. ......... 123 13.5.2.master receiver mode .............. .................................................. ........... 124 13.5.3.slave receiver mode ....... ............................................................. ......... 125 13.5.4.slave transmitter mode .... ............... ............................................. ......... 126 13.6.smbus status decoding ........................................................................ ......... 127 14. uart0................ ........................................................................................... ......... 131 14.1.enhanced baud rate g eneration.................. ................................................. 132 14.2.operational modes ....... ......................................................................... ......... 133 14.2.1.8-bit uart ........... ......................................................................... ......... 133 14.2.2.9-bit uart ........... ......................................................................... ......... 134 14.3.multiprocessor communications ... ........................................................ ......... 135 15. timers................ ............................................................ ............... .............. ........... 14 3 15.1.timer 0 and ti mer 1 ............... ............................................................... ......... 143 15.1.1.mode 0: 13-bit counter/timer ................. .............. ............... .................. 143 15.1.2.mode 1: 16-bit counter/timer ................. .............. ............... .................. 145 15.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 145 15.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 146 15.2.timer 2 ............. .................................................................................. ........... 151 15.2.1.16-bit timer with auto-rel oad............... ................................................. 151 15.2.2.8-bit timers with auto-rel oad............... ................................................. 152 16. programmable counter array ....... ............................................................. ......... 155 16.1.pca counter/timer ............. .................................................................. ......... 156 16.2.capture/compare modules ...... ............................................................. ......... 157 16.2.1.edge-triggered captur e mode................. .............. ............... .................. 158 16.2.2.software timer (compare) mode................. ................................. ......... 159 16.2.3.high speed output mode.............................................................. ......... 160 16.2.4.frequency output mode ....... ........................................................ ......... 161 16.2.5.8-bit pulse width modulato r mode............... ................................. ......... 162 16.2.6.16-bit pulse width modulat or mode ............. ................................. ......... 163 16.3.watchdog timer mode .... ...................................................................... ......... 164 16.3.1.watchdog timer operation ... ........................................................ ......... 164 16.3.2.watchdog timer usage ........ ........................................................ ......... 165 16.4.register descriptions for pca. ............... ............................................... ......... 167 17. c2 interface ................ .................................................................................. ......... 173 17.1.c2 interface registers......... .................................................................. ......... 173 17.2.c2 pin sharing ......... ............................................................................. ......... 175 document change list............... ...................................................................... ........ 176 contact information.......... ................................................................................ ........ 178
c8051f300/1/2/3/4/5 6 rev. 2.9 n otes :
rev. 2.9 7 c8051f300/1/2/3/4/5 list of figures 1. system overview figure 1.1. c8051f300/2 block di agram ........................................................ ......... 15 figure 1.2. c8051f301/3/4/5 blo ck diagram ............... ................................. ........... 15 figure 1.3. comparison of pe ak mcu execution speeds ......... ................. ............. 16 figure 1.4. on-chip clock and rese t ........................................................... ........... 17 figure 1.5. on-chip memory map (c8051f300/1/2/3 shown) ................. ................ 18 figure 1.6. development/in-syst em debug diagram................. ................. ............. 19 figure 1.7. digital cro ssbar diagram ............... ............................................. ........... 20 figure 1.8. pca block diagram ..... ............................................................... ........... 21 figure 1.9. pca block diagram ..... ............................................................... ........... 21 figure 1.10. 8-bit adc block diagr am ................ .......................................... ........... 22 figure 1.11. compar ator block diagram ........ ............................................... ........... 23 2. absolute maximum ratings 3. global electrical characteristics 4. pinout and package definitions figure 4.1. qfn-11 pinout diagr am (top view) .......... ................................. ........... 28 figure 4.2. qfn-11 package drawin g ................ .......................................... ........... 29 figure 4.3. typical qfn-11 sol der paste mask......... ................................. ............. 30 figure 4.4. typical qfn-11 landi ng diagram.............. ................................. ........... 31 figure 4.5. soic-14 pi nout diagram (top view) ... ......................................... ......... 32 figure 4.6. soic-14 pack age drawing ............... .......................................... ........... 33 figure 4.7. soic-14 pcb land patt ern ........................................................ ........... 34 5. adc0 (8-bit adc, c8051f300/2) figure 5.1. adc0 functional bl ock diagram.............. ................................. ............. 35 figure 5.2. typical temperatur e sensor transfer function..... ............ ........... ......... 37 figure 5.3. temperature sens or error with 1-point calib ration (vref = 2.40 v).... 38 figure 5.4. 8-bit adc track and conversion example timing .. ................. ............. 40 figure 5.5. adc0 equiva lent input circuits. ............... ................................. ............. 41 figure 5.6. adc window co mpare examples, si ngle-ended mode...... ............ ...... 45 figure 5.7. adc window com pare examples, differ ential mode .......... ............ ...... 46 6. voltage reference (c8051f300/2) figure 6.1. voltage reference functional block diagram ....... ............ ........... ......... 49 7. comparator0 figure 7.1. comparator0 functi onal block diagram .... ................................. ........... 51 figure 7.2. comparator hysteres is plot ........... ............................................. ........... 52 8. cip-51 microcontroller figure 8.1. cip-51 block diagram.. ............................................................... ........... 57 figure 8.2. program memory maps ............................................................... ........... 63 figure 8.3. data memory map..... .................................................................. ........... 64 9. reset sources figure 9.1. reset sources......... .................................................................. ............. 83 figure 9.2. power-on and vdd monitor reset timing ....... ............................ ......... 84
c8051f300/1/2/3/4/5 8 rev. 2.9 10. flash memory figure 10.1. flash program memo ry map.................. ................................. ............. 91 11. oscillators figure 11.1. oscillator diagram............... ........................................................ ......... 97 figure 11.2. 32.768 khz external crystal example...... ................................. ......... 101 12. port input/output figure 12.1. port i/o functional block diagram ................ ............................ ......... 103 figure 12.2. port i/o ce ll block diagram ............ .......................................... ......... 103 figure 12.3. crossbar priority decoder with xbr0 = 0x00 .. .................................. 104 figure 12.4. crossbar priority decoder with xbr0 = 0x44 .. .................................. 105 13. smbus figure 13.1. smbus block diagram ............. ................................................. ......... 111 figure 13.2. typical smbu s configuration .......... .......................................... ......... 112 figure 13.3. smbus transac tion ............. ............................................................... 113 figure 13.4. typical sm bus scl generation........ ................................................. 117 figure 13.5. typical ma ster transmitter sequence............. ................................... 123 figure 13.6. typical ma ster receiver sequence................. ................................... 124 figure 13.7. typical slave rece iver sequence............ ................................. ......... 125 figure 13.8. typical slave trans mitter sequence........ ................................. ......... 126 14. uart0 figure 14.1. uart0 block diagram ............. ................................................. ......... 131 figure 14.2. uart0 baud rate logic ............ ............................................... ......... 132 figure 14.3. uart interconnect di agram ............. ................................................. 133 figure 14.4. 8-bit uart tim ing diagram............ .......................................... ......... 133 figure 14.5. 9-bit uart timing diagram............ .......................................... ......... 134 figure 14.6. uart multi-proc essor mode interconne ct diagram .......... ................ 135 15. timers figure 15.1. t0 mode 0 bl ock diagram............... .......................................... ......... 144 figure 15.2. t0 mode 2 bl ock diagram............... .......................................... ......... 145 figure 15.3. t0 mode 3 bl ock diagram............... .......................................... ......... 146 figure 15.4. timer 2 16- bit mode block diagram .. ................................................ 151 figure 15.5. timer 2 8- bit mode block diagram .. ................. ............... .................. 152 16. programmable counter array figure 16.1. pca block diagram.... ............................................................... ......... 155 figure 16.2. pca counter /timer block diagram.... ................................................ 156 figure 16.3. pca interrupt blo ck diagram ................. ................................. ........... 157 figure 16.4. pca captur e mode diagram............. ................................................. 158 figure 16.5. pca software time r mode diagram ........ ................................. ......... 159 figure 16.6. pca high speed output mode diagram........... ............... .................. 160 figure 16.7. pca fr equency output mode ......... .......................................... ......... 161 figure 16.8. pca 8-bit pwm mode diagram .......... .............. ............... .................. 162 figure 16.9. pca 16-bit pwm mode ............................................................. ......... 163 figure 16.10. pca module 2 with watchdog ti mer enabled ..... ................. ........... 164 17. c2 interface figure 17.1. typical c2 pin shar ing.......... .................................................. ........... 175
rev. 2.9 9 c8051f300/1/2/3/4/5 list of tables 1. system overview table 1.1. product select ion guide ................. ............................................. ........... 14 2. absolute maximum ratings table 2.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 24 3. global electrical characteristics table 3.1. global electrical char acteristics ............ .............. ............... ........... ......... 25 4. pinout and package definitions table 4.1. pin definitions for the c8051f300/1/2/3/4/5 ................................ ........... 27 table 4.2. qfn-11 package dimensions ........... .......................................... ........... 29 table 4.3. qfn-11 landing diagram dimensions .. .............. ............... ........... ......... 31 table 4.4. soic-14 pack age dimensions ............ .......................................... ......... 33 table 4.5. soic-14 pcb land pattern dimensions ........... ............................ ......... 34 5. adc0 (8-bit adc, c8051f300/2) table 5.1. adc0 elec trical characteristics .... ............................................... ........... 47 6. voltage reference (c8051f300/2) table 6.1. external vo ltage reference circuit electrical characteristics ................ 50 7. comparator0 table 7.1. comparator0 electrical characteristics .... ................................. ............. 55 8. cip-51 microcontroller table 8.1. cip-51 instruction se t summary .............. ................................. ............. 59 table 8.2. special function regi ster (sfr) memory map ...... ............ ........... ......... 66 table 8.3. special functi on registers ................ .......................................... ........... 66 table 8.4. interrupt summ ary ................. ........................................................ ......... 74 9. reset sources table 9.1. user code space addr ess limits .......... .............. ............... ........... ......... 86 table 9.2. reset electric al characteristics ...... ............................................. ........... 86 10. flash memory table 10.1. f lash electric al characteristics ....... .......................................... ........... 90 table 10.2. security byte decodi ng .............. ............................................... ........... 91 11. oscillators table 11.1. internal oscillator el ectrical characteristics ...... ............... ........... ......... 99 12. port input/output table 12.1. port i/o dc electrical characteristics ............ ............................ ......... 110 13. smbus table 13.1. smbus clock source selection .............. ................................. ........... 116 table 13.2. minimum sda setup and hold times ...... ................................. ......... 117 table 13.3. sources for hardwa re changes to smb0cn ......... ................. ........... 121 table 13.4. smbus status decoding ............... ............................................. ......... 127 14. uart0 table 14.1. timer settings for standard baud rates ? using the internal 24.5 mhz oscillator ......... ............................ ......... 138 table 14.2. timer settings for standard baud rates ? using an external 25 mhz osc illator ............. ............................ ......... 138
c8051f300/1/2/3/4/5 10 rev. 2.9 table 14.3. timer settings for standard baud rates ? using an external 22.1184 mh z oscillator .... ............................ ......... 139 table 14.4. timer settings for standard baud rates ? using an external 18.432 mhz oscillator ...... ............................ ......... 140 table 14.5. timer settings for standard baud rates ? using an external 11.0592 mh z oscillator .... ............................ ......... 141 table 14.6. timer settings for standard baud rates ? using an external 3.6864 mhz oscillator ....... ................................... 142 15. timers 16. programmable counter array table 16.1. pca timebase input op tions ............ ................................................. 156 table 16.2. pca0cpm register settings for pca captur e/compare modules .... 157 table 16.3. watchdog timer timeout intervals ........... ................................. ......... 166 17. c2 interface
rev. 2.9 11 c8051f300/1/2/3/4/5 list of registers sfr definition 5.1. amx0sl: am ux0 channel select (c 8051f300/2) . . . . . . . . . . . . 42 sfr definition 5.2. adc0cf: adc0 configuration (c8051f 300/2) . . . . . . . . . . . . . . . 43 sfr definition 5.3. adc0: adc0 data word (c8051f300/2) . . . . . . . . . . . . . . . . . . . 43 sfr definition 5.4. adc0cn: adc0 control (c8051f 300/2) . . . . . . . . . . . . . . . . . . . . 44 sfr definition 5.5. adc0gt: adc0 greater-than data byte (c8051f300/2) . . . . . . 46 sfr definition 5.6. adc0lt: a dc0 less-than data byte (c80 51f300/2) . . . . . . . . . 46 sfr definition 6.1. ref0cn: reference control regist er . . . . . . . . . . . . . . . . . . . . . . 50 sfr definition 7.1. cpt0cn : comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 sfr definition 7.2. cpt0mx : comparator0 mux select ion . . . . . . . . . . . . . . . . . . . . 54 sfr definition 7.3. cpt0md : comparator0 mode selection . . . . . . . . . . . . . . . . . . . . 54 sfr definition 8.1. dpl: data pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 sfr definition 8.2. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 sfr definition 8.3. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 sfr definition 8.4. psw: program st atus word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 sfr definition 8.5. a cc: accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 sfr definition 8.6. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 sfr definition 8.7. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 sfr definition 8.8. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 sfr definition 8.9. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 77 sfr definition 8.10. eip1: extended inte rrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . . 78 sfr definition 8.11. it01cf: int0/int 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . 79 sfr definition 8.12. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 sfr definition 9.1. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 sfr definition 10.1. psctl: program store r/w contro l . . . . . . . . . . . . . . . . . . . . . . 92 sfr definition 10.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 10.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 11.1. oscicl : internal oscillator ca libration . . . . . . . . . . . . . . . . . . . . 98 sfr definition 11.2. oscicn: internal oscillator control . . . . . . . . . . . . . . . . . . . . . . 98 sfr definition 11.3. oscxcn: external oscillator c ontr ol . . . . . . . . . . . . . . . . . . . . 100 sfr definition 12.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 107 sfr definition 12.2. xbr1: port i/o crossbar regi ster 1 . . . . . . . . . . . . . . . . . . . . . 107 sfr definition 12.3. xbr2: port i/o crossbar regi ster 2 . . . . . . . . . . . . . . . . . . . . . 108 sfr definition 12.4. p0: port 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 sfr definition 12.5. p0mdin : port0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 sfr definition 12.6. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 110 sfr definition 13.1. smb0cf: smbus clock/configuration . . . . . . . . . . . . . . . . . . . 118 sfr definition 13.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 sfr definition 13.3. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 sfr definition 14.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 136 sfr definition 14.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 137 sfr definition 15.1. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 sfr definition 15.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 sfr definition 15.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
c8051f300/1/2/3/4/5 12 rev. 2.9 sfr definition 15.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 15.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 15.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 15.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 15.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 sfr definition 15.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 154 sfr definition 15.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 154 sfr definition 15.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 sfr definition 15.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 sfr definition 16.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 sfr definition 16.2. pca0md: pca mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 sfr definition 16.3. pc a0cpmn: pca capture/compare mode . . . . . . . . . . . . . . . 169 sfr definition 16.4. pca0l: pca counter/timer low byte . . . . . . . . . . . . . . . . . . . 170 sfr definition 16.5. pca0h: pca counter/timer high byte . . . . . . . . . . . . . . . . . . 170 sfr definition 16.6. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 171 sfr definition 16.7. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 171 c2 register definition 17.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 c2 register definition 17.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 173 c2 register definition 17.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 174 c2 register definition 17.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 174 c2 register definition 17.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 174
rev. 2.9 13 c8051f300/1/2/3/4/5 1. system overview c8051f300/1/2/3/4/5 devices are fully integrated mi xed-signal system-on-a-chip mcus. highlighted fea - tures are listed be low . refer to ta b l e 1.1 on page 14 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 8-bit 500 ksps 11-channel adc with programmable gain pre-amplifier and analog multiplexer ( c8051f300/2 only) ? precision programmable 25 mhz internal oscillator ? up to 8 kb of on-chip flash memory ? 256 bytes of on-chip ram ?smbus/i 2 c and enhanced uart serial interfaces implemented in hardware ? three general-purpose 16-bit timers ? programmable counter/timer array (pca) with three capture/compare modules and watchdog timer func tion ? on-chip power-on reset, v dd monitor, and temperature sensor ? on-chip voltage comparator ? byte-wide i/o port (5 v tolerant) with on-chip power-on reset, v dd monitor, watchdog timer, and clock oscillator, the c8051f300/1/2/3/4/5 devices are truly stand-alone s ystem-on-a-chip solutions. the flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. the on-chip silicon laboratories 2-wi re (c 2) development in terface allows non-intr usive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 2.7 to 3.6 v operation over the industrial temperature range (?45 to +85 c). th e port i/o and rst pins are tolerant of input signals up to 5 v. the c8051f300/1/2/3/4/5 are available in 3 x 3 mm 11-pin qfn or 14-pin soic packaging.
table 1.1. product selection guide ordering part number mips (peak) flash memory ram calibrated internal oscillator smbus/i 2 c uart timers (16-bit) programmable counter array digital port i/os 8-bit 500ksps adc temperature sensor analog comparators lead-free (rohs compliant) package c8051f300-gm 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? qfn-11 C8051F300-GS 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? soic-14 c8051f301-gm 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? qfn-11 c8051f301-gs 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? soic-14 c8051f302-gm 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? qfn-11 c8051f302-gs 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? soic-14 c8051f303-gm 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? qfn-11 c8051f303-gs 25 8 k 256 ? ? ? 3 ? 8 ? ? 1 ? soic-14 c8051f304-gm 25 4 k 256 ? ? ? 3 ? 8 ? ? 1 ? qfn-11 c8051f304-gs 25 4 k 256 ? ? ? 3 ? 8 ? ? 1 ? soic-14 c8051f305-gm 25 2 k 256 ? ? ? 3 ? 8 ? ? 1 ? qfn-11 c8051f305-gs 25 2 k 256 ? ? ? 3 ? 8 ? ? 1 ? soic-14 c8051f300/1/2/3/4/5 14 rev. 2.9
port 0 latch uart 8k/4k/2k byte flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1 pca/ wdt p 0 d r v x b a r port i/o mode & config. xbar control reset xtal1 xtal2 external oscillator circuit system clock precision internal oscillator clock & reset configuration analog/digital power debug hw smbus x2 x4 x2 c2d c2d cp0 + - cp0 p0.0/vref p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6 p0.7/c2d vdd gnd /rst/c2ck brown- out port 0 latch uart 8kbyte flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1 pca/ wdt 8-bit 500ksps adc a m u x ain0-ain7 p 0 d r v vref x b a r port i/o mode & config. xbar control reset xtal1 xtal2 external oscillator circuit system clock precision internal oscillator clock & reset configuration analog/digital power debug hw vdd adc config. & control smbus x2 x4 x2 c2d c2d cp0 pga + - temp cp0 p0.0/vref p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/c2d vdd gnd /rst/c2ck brown- out vdd cnvstr rev. 2.9 15 c8051f300/1/2/3/4/5 figure 1.1. c8051f300/2 block diagram figure 1.2. c8051f301/3/4/5 block diagram
c8051f300/1/2/3/4/5 16 rev. 2.9 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f300/1/2/3/4/5 fam ily utilizes silicon labs' proprietary ci p-51 microcontr oller core. the cip-51 is fully compatible with the mcs- 51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the cip-51 core offers all the peripherals included with a standard 8052, including two standard 16-bit coun ter/timers, one enhanced 16-bit coun ter/timer with exte rnal oscillator input, a full-duplex uart with extended baud rate config uration, 256 bytes of internal ram, 128 byte spe - cial function register (sfr) addres s space, and a byte-wide i/o port. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 mhz. by contrast, the cip-51 core exe - cutes 70% of its instructions in one or two system clock cy cles, with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table be low shows the total number of instructions that require each execution time. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. figure 1.3 shows a comparison of peak throughputs for variou s 8 -bit microcontroller cores with their maximum sys - tem clocks. figure 1.3. comparison of peak mcu execution speeds clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 5 10 15 20 aduc812 8051 (16 mhz clk) philips 80c51 (33 mhz clk) microchip pic17c75x (33 mhz clk) silicon labs cip-51 (25 mhz clk) mips 25
rev. 2.9 17 c8051f300/1/2/3/4/5 1.1.3. additional features the c8051f300/1/2/3/4/5 soc family includes several key enhancements to the cip-51 core and periph - erals to improve performance and ea se of use in en d applications. the extended interrupt handler provi des 12 inte rrupt sources into the cip-51 (as opposed to 7 for the stan - dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. an interrupt driven sys tem requires less interv ention by the mcu, giving it more effe ctive throughput. the extra interrupt sources are very useful when build ing multitasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor (forces reset when power supply voltage drops below 2.7 v), a watchdog timer, a missing clock detector, a voltage le vel detection from comparator0, a forced software reset, an external reset pin, and an illegal flash read/write protection circuit. each reset source except for the por, reset input pin, or flash protection may be disabled by the user in software. the wdt may be permanently enabled in software after a power- on reset during mcu initialization. the internal oscillator is ava ila ble as a factory calibrated 24.5 mhz 2% (c8051f300/1 devices); an uncal - ibrated version is available on c8051f302/3/4/5 device s. on all c8051f300/1/2/3/ 4/5 devices, the internal oscillator period may be user programm ed in ~0.5% increments. an external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, rc, or cmos clock source to generate the system clock. if desired, the system clock source may be switched on-the-fly to the ex ternal oscillator circuit. an external oscillator can be extremely useful in low power ap plications, allowing the mcu to run from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25 mhz) in ternal oscillator as needed. figure 1.4. on-chi p clock and reset pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel p0.x p0.y en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable xtal1 xtal2 external oscillator drive illegal flash operation + - comparator 0 c0rsef /rst (wired-or) power on reset + - vdd supply monitor enable '0'
c8051f300/1/2/3/4/5 18 rev. 2.9 1.2. on-chip memory the cip-51 has a standard 8051 program and data addr ess configuration. it in cludes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr addre ss space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 byte s can be byte addressable or bit addressable. the c8051f300/1/2/3 includes 8k bytes of flash prog r am memory (the c8051f304 includes 4k bytes; the c8051f305 includes 2k bytes). this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. see figure 1.5 for the c8051f300/1/ 2/3 system memory map. figure 1.5. on-chip memory map (c8051f300/1/2/3 shown) program memory (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space 8k bytes flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x1e00 0x1dff
rev. 2.9 19 c8051f300/1/2/3/4/5 1.3. on-chip debug circuitry the c8051f300/1/2/3/4/ 5 devices include on-chip silicon labs 2-wire (c2) debug circuitry that provides non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application. silicon labs' debugging syst em support s inspection and modificati on of memory and registers, break - points, and single stepping. no additional target ram, pr ogram memory, timers, or communications chan - nels are required. all the digital and analog periphera ls are functional and work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the c8051f300dk development kit provides all the har dwar e and software necessary to develop applica - tion code and perform in-circuit debugging with the c8 051f300/1/2/3/4/5 mcus. the kit includes software with a developer's studio and debugger, an integrated 80 51 assembler, and a c2 debug adapter. it also has a target application board with the associated mcu installed and large prototyping area, plus the nec - essary communication cables and wall-mount power supply. the development kit requires a computer with w indows? 98 se or later. the s ilicon labs ide interface is a vastly superior developing and debug - ging configuration, compared to standard mcu emulat or s that use onboard "ice chips" and require the mcu in the application bo ard to be socketed. silicon labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. figure 1.6. development/in -system debug diagram 1.4. programmable digital i/o and crossbar c8051f300/1/2/3/4/5 devices include a byte-wide i/o po rt that behaves like a typical 8051 port with a few enhancements. each port pin may be configured as an analog input or a digital i/o pin. pins selected as digital i/os may additionally be configured for push-p ull or open-drain output. the ?weak pull-ups? that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. target pcb rs-232 vdd gnd c2 (x2), vdd, gnd windows 98 se or later silicon labs integrated development environment c8051f300 debug adapter
c8051f300/1/2/3/4/5 20 rev. 2.9 perhaps the most unique port i/o enhancement is the dig ital crossbar. this is essentially a digital switch - ing network that allows mapping of internal di git al system resources to port i/o pins (see figure 1.7 ). on- chip counter/timers, serial buses, hw interrupts, comparator output, and other digital signals in the control - ler can be configured to appear on the port i/o pins sp ecified in the crossba r cont rol registers. this allows the user to select the exact mix of general purpose po rt i/o and digital resource s needed for the particular application. figure 1.7. digital crossbar diagram 1.5. serial ports the c8051f300/1/2/3/4/5 family includes an smbus/i 2 c interface and a full-duplex uart with enhanced baud rate configuration. each of the serial buses is fully implemented in ha rdware and makes extensive use of the cip-51's interrupts, thus requiring very little cpu intervention. xbr0, xbr1, xbr2 registers digital crossbar priority decoder sysclk 2 2 (internal digital signals) highest priority lowest priority p0 i/o cells p0.0 p0.7 8 p0mdout, p0mdin registers smbus uart t0, t1 2 4 pca p0 port latch (p0.0-p0.7) 8 cp0 outputs 2
rev. 2.9 21 c8051f300/1/2/3/4/5 1.6. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the three 16-bit general purpose counter/timers. the pca consists of a dedica ted 16-bit counter/timer time base with three pro - grammable capture/compare modules. the pca clock is der ived from one of six sources: the system clock divided by 12, the system clock divided by 4, timer 0 overflows, an external cl ock input (eci), the system clock, or the external osc illator clock source divided by 8. the extern al clock source selection is useful for real-time clock functi onality, where the pca is clocked by an exte rnal source while the internal oscillator drives the system clock. each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, sof tware timer, high speed output, 8- or 16-bit pulse width modulator, or frequency output. additionally, capture/compare module 2 offers watchdog timer (wdt) capabilit ies. following a system reset, module 2 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. figure 1.9. pc a block diagram 16-bit counter/timer cex1 eci digital crossbar cex2 cex0 port i/o capture/compare module 1 capture/compare module 0 capture/compare module 2 pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8
c8051f300/1/2/3/4/5 22 rev. 2.9 1.7. 8-bit analog to digital converter (c8051f300/2 only) the c8051f300/2 includes an on-chip 8-bit sar adc with a 10-channel differential input multiplexer and programmable gain amplifier. with a maximum throughput of 500 ksps, the adc offers true 8-bit accuracy with an inl of 1lsb. the adc system includes a c onfigurable analog multiplexe r that selects both posi - tive and negative adc inputs. each port pin is avail able as an adc input; additionally, the on-chip temper - ature sensor output and the power supply voltage (v dd ) are available as adc inputs. user firmware may shut down the adc to save power. the integrated programmable gain amplifier (pga) amplif ie s the adc input by 0.5, 1, 2, or 4 as defined by user software. the gain stage is especially useful wh en different adc input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc offset. conversions can be started in five wa ys: a software command, an overflow of timer 0, 1, or 2, or an exter - nal convert start signal. this flexibilit y allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external hw signal s. conversion completions are indicated by a status bit and an interrupt (if enabled). the resulting 8-bit da ta word is latched into an sfr upon completion of a conversion. window compare registers for the adc data can be conf igu red to interrupt the co ntroller when adc data is either within or outside of a specified range. the adc can monitor a key voltage continuously in back - ground mode, but not interrupt the controller unless the converted data is within/outside the specified range. figure 1.10. 8-bit adc block diagram x vdd 8 9-to-1 amux temp sensor 10-to-1 amux vdd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 dgnd programmable gain amplifier start conversion window compare logic window compare interrupt + - configuration, control, and data registers analog multiplexer t0 overflow tmr2 overflow t1 overflow software write external convert start 8-bit sar adc end of conversion interrupt adc data register
rev. 2.9 23 c8051f300/1/2/3/4/5 1.8. comparator c8051f300/1/2/3/4/5 devices include an on-chip voltag e comparator that is e nabled/disabled and config - ured via user software. all port i/o pins may be configurated as comparator inputs. two comparator out - puts may be routed to a port pin if desired: a la tc hed output and/or an unlatched (asynchronous) output. comparator response time is programmable, allowi ng the user to select between high-speed and low- power modes. positive and negative hysteresis is also configurable. comparator interrupts may be generated on rising, falling, or both edges. when in idle mode, these inter - rupts may be used as a ?wake-up? source. the compar ato r may also be configured as a reset source. figure 1.11. comparator block diagram reset decision tree + - crossbar interrupt handler q q set clr d q q set clr d (synchronizer) gnd cp0 + p0.0 p0.2 p0.4 p0.6 cp0 - p0.1 p0.3 p0.5 p0.7 vdd
c8051f300/1/2/3/4/5 24 rev. 2.9 2. absolute maximum ratings table 2.1. absolute maximum ratings* parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? 5.8 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd and gnd ? ? 500 ma maximum output current sunk by rst or any port pin ? ? 100 ma *note: stresses above those listed under ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
rev. 2.9 25 c8051f300/1/2/3/4/5 3. global electrical characteristics table 3.1. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply voltage v rst 1 3.0 3.6 v digital supply ram data retention voltage ?1.5? v sysclk (system clock) (note 2) 0?25mhz t sysh (sysclk high time) 18 ? ? ns t sysl (sysclk low time) 18 ? ? ns specified operating ? temperature range ?40 ? +85 c digital supply current?cpu active (normal mode, fetching instructions from flash) i dd (note 3) v dd = 3.6 v, f = 25 mhz ? 9.4 10.2 ma v dd = 3.0 v, f = 25 mhz ? 6.6 7.2 ma v dd = 3.0 v, f = 1 mhz ? 0.45 ? ma v dd = 3.0 v, f = 80 khz ? 36 ? a i dd supply sensitivity (note 3) f = 25 mhz ? 69 ? %/v f = 1 mhz ? 51 ? %/v i dd frequency sensitivity (note 3, note 4) v dd = 3.0 v, f <= 15 mhz, t = 25 c ? 0.45 ? ma/mhz v dd = 3.0 v, f > 15 mhz, t = 25 c ? 0.16 ? ma/mhz v dd = 3.6 v, f <= 15 mhz, t = 25 c ? 0.69 ? ma/mhz v dd = 3.6 v, f > 15 mhz, t = 25 c ? 0.20 ? ma/mhz digital supply current?cpu inactive (idle mode , not fetching instructions from flash) i dd (note 3) v dd = 3.6 v, f = 25 mhz ? 3.3 4.0 ma v dd = 3.0 v, f = 25 mhz ? 2.5 3.2 ma v dd = 3.0 v, f = 1 mhz ? 0.10 ? ma v dd = 3.0 v, f = 80 khz ? 8 ? a
c8051f300/1/2/3/4/5 26 rev. 2.9 i dd supply sensitivity (note 3) f = 25 mhz ? 47 ? %/v f = 1 mhz ? 59 ? %/v i dd frequency sensitivity (note 3, note 5) v dd = 3.0 v, f <= 1 mhz, t = 25 c ? 0.27 ? ma/mhz v dd = 3.0 v, f > 1 mhz, t = 25 c ? 0.10 ? ma/mhz v dd = 3.6 v, f <= 1 mhz, t = 25 c ? 0.35 ? ma/mhz v dd = 3.6 v, f > 1 mhz, t = 25 c ? 0.12 ? ma/mhz digital supply current ? (stop mode, shutdown) oscillator not running, v dd monitor disabled ?< 0.1? a notes: 1. gi ven in table 9.2 on page 86 . 2. sysclk m ust be at least 32 khz to enable debugging. 3. based on device characterization data; not production tested. 4. normal idd can be estimated for freq uencies <= 15 mhz by simply multiplying th e freq uency of interest by the frequency sensitivity number for that r ange. when using these numbers to estimate i dd for >15 mhz, the estimate sho uld be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity numbe r. ? for example: v dd = 3.0 v; f = 20 mhz, i dd = 6.6 ma ? (25 mhz ? 20 mhz) x 0.16 ma/mhz = 5.8 ma. 5. id le idd can be estimated for frequencies <= 1 mhz by simply multiplying the frequency of interest by the fre quency sensitivity number for that range. wh en using these numbers to estimate idle i dd for >1 mhz, the estimate sho uld be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity numbe r. ? for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 3.3 ma ? (25 mhz ? 5 mhz) x 0.10 ma/mhz = 1.3 ma. table 3.1. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units
rev. 2.9 27 c8051f300/1/2/3/4/5 4. pinout and package definitions table 4.1. pin definitions for th e c8051f300/1/2/3/4/5 name pin f300/1/2/3/4/5 gm pin f300/1/2/3/4/5 gp type description vref / p0.0 1 5 a in d i/o or a in external voltage reference input. port 0.0. see section 12 for complete des cription. p0.1 2 6 d i/o or a in port 0.1. see section 12 for complete des cription. v dd 3 7 power supply voltage. xtal1 / p0.2 4 8 a in d i/o or a in crystal input. this pin is the external oscillator cir - cuit return for a crystal or ceramic resonator. see section 11.2 . port 0.2. see section 12 for complete des cription. xtal2 / p0.3 5 10 a out d i/o crystal input/output. for an external crystal or res - onator, this pin is the excitation driver. this pin is the exter nal clock input fo r cmos, capacitor, or rc network configurations. see section 11.2 . port 0.3. see section 12 for complete des cription. p0.4 6 12 d i/o or a in port 0.4. see section 12 for complete des cription. p0.5 7 13 d i/o or a in port 0.5. see section 12 for complete des cription. c2ck / rst 8 14 d i/o d i/o clock signal for the c2 develo pment interface. device reset. open-drain output of internal por or v dd monitor. an external so urce can initiate a sys - tem reset by driving this pin low for at least 10 s. p0.6 / cnvstr 9 1 d i/o or a in d i/o port 0.6. see section 12 for complete des cription. adc external convert start input strobe. c2d / p0.7 10 2 d i/o d i/o or a in data signal for the c2 development interface. port 0.7. see section 12 for complete des cription. gnd 11 3 ground. n.c. pins for f30x gp packages: 4, 9, 11
c8051f300/1/2/3/4/5 28 rev. 2.9 figure 4.1. qfn-11 pi nout diagram (top view) vref / p0.0 p0.1 vdd xtal1 / p0.2 xtal2 / p0.3 p0.4 p0.5 c2ck / /rst p0.6 / cnvstr c2d / p0.7 gnd
rev. 2.9 29 c8051f300/1/2/3/4/5 figure 4.2. qfn-11 package drawing table 4.2. qfn-11 package dimensions dimension min nom max dimension min nom max a 0.80 0.90 1.00 e 3.00 bsc. a1 0.03 0.07 0.11 e2 2.20 2.25 2.30 a3 0.25 ref l .45 .55 .65 b 0.18 0.25 0.30 aaa -- -- 0.15 d 3.00 bsc. bbb -- -- 0.15 d2 1.30 1.35 1.40 ddd -- -- 0.05 e 0.50 bsc. eee -- -- 0.08 notes: 1. all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. dimen sioning and tolerancing per ansi y14.5m-1994. 3. th is drawing conforms to jedec outline mo-243, vari ation veed except for custom features d2, e2, and l which are toleranced per supplier designation. 4. reco mmended card reflow profile is per the je dec/ipc j-std-020c specif ication for small body components.
c8051f300/1/2/3/4/5 30 rev. 2.9 figure 4.3. typical qfn-11 solder paste mask 0.50 mm lt e e d e lb k d2 b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm 0.30 mm 0.20 mm 0.60 mm 0.70 mm d4 b 0.30 mm 0.35 mm e2 0.20 mm
rev. 2.9 31 c8051f300/1/2/3/4/5 . figure 4.4. typical qfn-11 landing diagram table 4.3. qfn-11 landing diagram dimensions dimension min max c1 2.75 2.85 c2 2.75 2.85 e 0.50 bsc x1 0.20 0.30 x2 1.40 1.50 y1 0.65 0.75 y2 2.30 2.40 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. ? notes: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. ? notes: s tencil design 1. a st ainless steel, laser-cut and electro-polished st encil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 3 x 1 array of 1.30 x 0.60 mm openings on 0.80 mm pitch should be used for the center gro und pad. ? notes: card assembly 1. a no-cle an, type-3 solder paste is recommended. 2. t he recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
c8051f300/1/2/3/4/5 32 rev. 2.9 figure 4.5. soic-14 pinout diagram (top view) 2 1 4 3 5 6 7 13 14 11 12 10 9 8 top view c2d/p0.7 p0.6 gnd n/c p0.0 p0.1 vdd p0.3 p0.5 c2ck/rst p0.4 n/c n/c p0.2
rev. 2.9 33 c8051f300/1/2/3/4/5 figure 4.6. soic- 14 package drawing table 4.4. soic-14 package dimensions dimension min max dimension min max a - - - 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc b 0.33 0.51 q 0 ? 8 ? c 0.17 0.25 aaa 0.10 d 8.65 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. al l dimensions shown are in millimeters (mm). 2. dimensio ning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline ms012, variation ab. 4. recommend ed card reflow profile is per th e jedec/ipc j-std-020c specification for small body components.
c8051f300/1/2/3/4/5 34 rev. 2.9 figure 4.7. soic-14 pcb land pattern table 4.5. soic-14 pcb land pattern dimensions dimension min max c1 5.30 5.40 e 1.27 bsc x1 0.50 0.60 y1 1.45 1.55
rev. 2.9 35 c8051f300/1/2/3/4/5 5. adc0 (8-bit adc, c8051f300/2) the adc0 subsystem for the c8051f300 /2 consists of two analog multiple xers (referred to collectively as amux0) with 11 total input select ions, a differential programmable gain amplifier (pga), and a 500 ksps, 8- bit su ccessive-approximation-register adc with integrated track-and-hold and programmable window detector (see block diagram in figure 5.1 ). the amux0, pga, data conversion modes, and window detec - tor are all configurable under software contro l via the s pecial function registers shown in figure 5.1 . adc0 operates in both single-ended and differential modes, and may be configured to measure any port pin , the temperature sensor output, or v dd with respect to any port pin or gnd. the adc0 subsystem is enabled only when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1. the adc0 sub - system is in low power shutdown when this bit is logic 0. amux0 + - x vdd adc0cf amp0gn0 amp0gn1 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 8-bit sar adc ref 8 sysclk adc0 16 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0gt adc0lt 9-to-1 amux ad0wint temp sensor 10-to-1 amux vdd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 gnd 001 010 011 1xx cnvstr input comb. logic amx0sl amx0p0 amx0p1 amx0p2 amx0n3 amx0n2 amx0n1 amx0n0 amx0p3 figure 5.1. adc0 functional block diagram
c8051f300/1/2/3/4/5 36 rev. 2.9 5.1. analog multiplexer and pga the analog multiplexers (amux0) select the positive an d negative inputs to the pga, allowing any port pin to be measured relative to any other port pin or gnd. additionally, the on-chip temperature sensor or the positive power supply (v dd ) may be selected as the positive pga input. when gnd is selected as the negative input, adc0 operates in single-ended mode; al l other times, adc0 operates in differential mode. the adc0 input channels are selected in the amx0sl register as described in sfr definition 5.1 . the conversion code format differs in single-ended ve rsus dif ferential modes, as shown below. when in single-ended mode (negative input is selected gnd), conversion codes are represented as 8-bit unsigned integers. inputs are measured from ?0? to vref x 255/256. example codes are shown below. input voltage adc0 output (conversion code) vref x 255/256 0xff vref x 128/256 0x80 vref x 64/256 0x40 0 0x00 when in differential mode (negativ e input is not selected as gnd), co nversion codes are represented as 8-bit signed 2s complement numbers. inputs are measured from ?vref to vref x 127/128. example codes are shown below. input voltage adc0 output (conversion code) vref x 127/128 0x7f vref x 64/128 0x40 0 0x00 ?vref x 64/128 0xc0 ?vref 0x80 important note about adc0 input configuration: port pins selected as adc0 inputs should be config - ured as analog inputs and should be skipped by the digit a l crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register p0mdin. to force the crossbar to skip a port pin, set to ?1? the corresponding bit in register xbr0. see section ?12. port input/output? on page 103 for more port i/o configuration details. the pga amplifies the amux0 output signal as defined b y the amp0gn1-0 bits in the adc0 configuration register ( sfr definition 5.2 ). the pga is software-programmable for gain s of 0.5, 1, 2, or 4. the gain defaults to 0.5 on reset. 5.2. temperature sensor the typical temperature sensor transfer function is shown in figure 5.2. the output voltage (v temp ) is the positive pga input when the temperature sensor is se le ct ed by bits amx0p2-0 in register amx0sl; this voltage will be amplified by th e pga according to the user -programmed pga settings.
0 -50 50 100 (celsius) v temp = 3.35*(temp c ) + 897 mv 700 800 900 1000 1100 (mv) 1200 rev. 2.9 37 c8051f300/1/2/3/4/5 figure 5.2. typical temperatur e sensor transfer function the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea - surements (see ta b l e 5.1 for linearity specificatio n s ). for absolute temperature measurements, gain and/ or offset calibration is recomme nd ed. t ypically a 1-point calibration includes the following steps: step 1. control/measure the ambient temper atur e ( this temperature must be known). step 2. power the device, and delay for a few seconds to allow for self-heating. step 3. perform an adc conversion with the te mperature sensor selected as the positive input and gnd selected as the negative input. step 4. calculate the offset and/or gain characte ristics, and store these values in non-volatile memory for use with subsequent te mperature sensor measurements. figure 5.3 shows the typical temperature sensor er ror assumin g a 1-point calibration at 25 c. note that p arameters which affect adc measurement, in particular the voltage reference value, will also a ff ect temperature measurement.
-40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 c8051f300/1/2/3/4/5 38 rev. 2.9 figure 5.3. temperature sensor error with 1-point calibration (vref = 2.40 v)
rev. 2.9 39 c8051f300/1/2/3/4/5 5.3. modes of operation adc0 has a maximum conversion speed of 500 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register (system clock divided by (ad0sc + 1) for 0 ? ad0sc ? ? 31). 5.3.1. starting a conversion a conversion can be initiated in one of five ways, dep ending on the programmed states of the adc0 start of conversion mode bits (ad0cm2?0) in register adc0 cn. conversions may be initiated by one of the fol - lowing: 1. writing a ?1? to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e. timed continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal (pin p0.6) writing a ?1? to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to lo gic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion completions, the adc0 in terrupt flag (ad0int) should be used. converted data is available in the a dc0 data register, adc0, when bit ad0int is logic 1. note that when timer 2 overflows are used as the conversion source, timer 2 low byte overflows are used if timer 2 is in 8-bit mode; timer 2 high byte overflows are used if timer 2 is in 16-bit mode. see sec - tion ?15. timers? on page 143 for timer configuration. important note about using cnvstr: th e cnvstr input pin also functi ons as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0.6, set to ?1? bit6 in register xbr0. see section ?12. port input/output? on page 103 for details on port i/o configuration.
c8051f300/1/2/3/4/5 40 rev. 2.9 5.3.2. tracking modes according to table 5.1 on page 47, each adc0 conversion must be pr ec eded by a minimum tracking time for the converted result to be accurate. the ad0tm bit in regis t er adc0cn cont rols the adc0 track-and- hold mode. in its default state, the adc0 input is c ontinuously tracked except when a conversion is in prog - ress. when the ad0tm bit is logic 1, adc0 operates in low- powe r track-and-ho ld mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signal). when the cnvstr signal is used to initiate conversions in low-power tracking mode, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.4 ). tracking can also be disabled (shutdown) when the device is in low po wer st andby or sleep modes. low-power track- and-hold mode is also useful when am ux or pga settings are frequently changed, due to the settling time requirements described in section ?5.3.3. settling time requirements? on page 41 . write '1' to ad0busy, timer 0, timer 2, timer 1 overflow (ad0cm[2:0]=000, 001, 010, 011) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks sar clocks b. adc timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=1xx) ad0tm=1 a. adc timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 10 11 12 123456789 10 11 12 123456789 10 11 12 13 14 15 figure 5.4. 8-bit adc track a nd conversion example timing
rev. 2.9 41 c8051f300/1/2/3/4/5 5.3.3. settling time requirements when the adc0 input configuration is changed (i.e., a different amux0 or pga selection is made), a mini - mum tracking time is required before an accurate conv e r sion can be performed. this tracking time is deter - mined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the a c curacy required for the conversion. note that in lo w-power tracking mode, three sar clocks are used for tracking at the start of every conv ersion. for most applications, these three sar clocks will meet the mini - mum tracking time requirements. figure 5.5 shows the equivalent adc0 input circuits for b o th differential and single-ended modes. notice that the equivalent time constant for both input circ uit s is the same. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1 . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b l e 5.1 for adc0 minimum settling time (track/hold time) requirements. t 2 n sa ------ - ?? ?? r total c sample ? equation 5.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (8). r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 5pf c sample = 5pf mux select mux select differential mode p0.x p0.y r mux = 5k c sample = 5pf rc input = r mux * c sample mux select single-ended mode p0.x note: when the pga gain is set to 0.5, c sample = 3pf figure 5.5. adc0 eq uivalent input circuits
c8051f300/1/2/3/4/5 42 rev. 2.9 sfr definition 5.1. amx0sl: amux0 channel select (c8051f300/2) bits7?4: amx0n3?0: amux0 negative input selection. note that when gnd is selected as the nega tive input, adc0 operates in single-ended mode. for all other negative input select ions, adc0 operates in differential mode. 0000?1000b: adc0 negative input selected per the chart below. bits3?0: amx0p3?0: amux0 positive input selection. 0000?1001b: adc0 positive input selected per the chart below. 1010?1111b: reserved. r/w r/w r/w r/w r/w r/w r/w r/w reset value amx0n3 amx0n2 amx0n1 amx0n0 amx0 p3 amx0p2 amx0p1 amx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb amx0n3?0 adc0 negative input 0000 p0.0 0001 p0.1 0010 p0.2 0011 p0.3 0100 p0.4 0101 p0.5 0110 p0.6 0111 p0.7 1xxx gnd (adc in single-ended mode) amx0p3?0 adc0 positive input 0000 p0.0 0001 p0.1 0010 p0.2 0011 p0.3 0100 p0.4 0101 p0.5 0110 p0.6 0111 p0.7 1000 temperature sensor 1001 v dd
rev. 2.9 43 c8051f300/1/2/3/4/5 sfr definition 5.2. adc0cf: adc0 confi guration (c8051f300/2) bits7?3: ad0sc4?0: adc0 sar c onversion clock period bits. sar conversion clock is derived from sys tem clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4-0. sar conversion clock requirements are given in table 5.1. bit2: unused. read = 0b ; write = don?t care. bits1?0: amp0gn1?0: adc0 internal amplifier gain (pga). 00: gain = 0.5 01: gain = 1 10: gain = 2 11: gain = 4 r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 ? amp0gn1 amp0gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc ad 0 sc sysclk clk sar ----------- ---------- - 1? = sfr definition 5.3. adc0: adc0 data word (c8051f300/2) bits7?0: adc0 data word. adc0 holds the output data byte from the last adc0 conversion. when in single-ended mode, adc0 holds an 8-bit unsigned integer. when in differential mode, adc0 holds a 2?s complement signed 8-bit integer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe
c8051f300/1/2/3/4/5 44 rev. 2.9 sfr definition 5.4. adc0cn: adc0 control (c8051f300/2) bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc0 track mode bit. 0: normal track mode: when adc0 is enabled , tracking is continuous unless a conversion is in progress. 1: low-power track mode: tracking defined by ad0cm2-0 bits (see below). bit5: ad0int: adc0 conversion complete interrupt flag. 0: adc0 has not completed a data conversi on since the last time ad0int was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: unused. write: 0: no effect. 1: initiates adc0 conversion if ad0cm2-0 = 000b bit3: ad0wint: adc0 window compare interrupt flag. 0: adc0 window comparison data match has not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bits2?0: ad0cm2-0: adc0 start of conversion mode select. when ad0tm = 0: 000: adc0 conversion initiated on every write of ?1? to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiat ed on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 1. 1xx: adc0 conversion initiated on rising edge of external cnvstr. when ad0tm = 1: 000: tracking initiated on write of ?1? to ad 0busy and lasts 3 sar clocks, followed by con- version. 001: tracking initiated on overflow of timer 0 and lasts 3 sar clocks, followed by conver- sion. 010: tracking initiated on overflow of timer 2 and lasts 3 sar clocks, followed by conver- sion. 011: tracking initiated on overflow of timer 1 and lasts 3 sar clocks, followed by conver- sion. 1xx: adc0 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0wi nt ad0cm2 ad0cm1 ad0cm0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8
rev. 2.9 45 c8051f300/1/2/3/4/5 5.4. programmable window detector the adc programmable window detector continuously compares the adc0 output to user-programmed limits, and notifies the system when a desired condition is detected. this is especially effective in an inter - rupt-driven system, saving code spac e and cp u bandwidth while deliverin g faster system response times. the window detector interrup t flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gt) and less-than (adc0lt) registers hold the comparison values. example comparisons for single-ended and differential modes are shown in figure 5.6 and figure 5.7 , respectively. notice that the window detector flag can be programmed to indicate when measured data is inside or out - side of the user-programmed limits depending on the contents of the adc0lt and adc0gt registers. 5.4.1. window detector in single-ended mode figure 5.6 shows two example window comparison s fo r single-ended mode, with adc0lt = 0x20 and adc0gt = 0x10. notice that in single-end e d mode, the codes vary from 0 to vref x (255/256) and are represented as 8-bit unsig ned integers. in the left example, an ad0wint interr upt will be genera ted if the adc0 conversion word (adc0) is within the range defined by adc0gt and adc0lt (if 0x10 ? adc0 ? 0x20). in the right example, and ad0wint interrup t will be generated i f adc0 is outside of the range defined by adc0gt and adc0lt (if adc0 ? 0x10 or adc0 ? 0x20). 0xff 0x21 0x20 0x1f 0x11 0x10 0x0f 0x00 0 input voltage (p0.x - gnd) ref x (255/256) ref x (32/256) ref x (16/256) ad0wint=1 ad0wint not affected ad0wint not affected adc0lt adc0gt 0xff 0x21 0x20 0x1f 0x11 0x10 0x0f 0x00 0 input voltage (p0.x - gnd) ref x (255/256) ref x (32/256) ref x (16/256) ad0wint not affected adc0gt adc0lt ad0wint=1 ad0wint=1 adc0 adc0 figure 5.6. adc window compare examples , single-ended mode
c8051f300/1/2/3/4/5 46 rev. 2.9 5.4.2. window detector in differential mode figure 5.7 shows two example window comparison s for dif ferential mode, with adc0lt = 0x10 (+16d) and adc0gt = 0xff (?1d). notice that in differential mode, the codes vary from ?vref to vref x (127/128) a nd are represented as 8-bit 2?s complement signed integers. in the left example, an ad0wint interrupt will be generated if the adc0 conv ersion word (adc0l) is within th e range defined by adc0gt and adc0lt (if 0xff (?1d) < adc0 < 0x10 (16d)). in the right example, an ad0wint interr upt w ill be gener - ated if adc0 is outside of the rang e define d by adc0gt and adc0lt (if adc0 < 0xff (?1d) or adc0 > 0x10 (+16d)). 0x7f (127d) 0x11 (17d) 0x10 (16d) 0x0f (15d) 0x00 (0d) 0xff (-1d) 0xfe (-2d) 0x80 (-128d) -ref input voltage (p0.x - p0.y) ref x (127/128) ref x (16/128) ref x (-1/256) 0x7f (127d) 0x11 (17d) 0x10 (16d) 0x0f (15d) 0x00 (0d) 0xff (-1d) 0xfe (-2d) 0x80 (-128d) -ref input voltage (p0.x - p0.y) ref x (127/128) ref x (16/128) ref x (-1/256) ad0wint=1 ad0wint not affected ad0wint not affected adc0lt adc0gt ad0wint not affected adc0gt adc0lt ad0wint=1 ad0wint=1 adc0 adc0 figure 5.7. adc window comp are examples, di fferential mode sfr definition 5.5. adc0gt: adc0 greater-tha n data byte (c8051f300/2) bits7?0: adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 sfr definition 5.6. adc0lt: adc0 less-than data byte (c8051f300/2) bits7?0: adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6
table 5.1. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl = 0), pga gain = 1, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb offset error ?5.0 0.5 5.0 lsb full scale error differential mode ?5.0 ?1 5.0 lsb dynamic performance (10 khz sine-wave differential input, 1 db below full scale, 500 ksps) signal-to-noise plus distortion 45 48 ? db total harmonic distortion up to the 5 th harmonic ? ?56 ? db spurious-free dynamic range ? 58 ? db conversion rate sar conversion clock ? ? 6 mhz conversion time in sar clocks 11 ? ? clocks track/hold acquisition time 300 ? ? ns throughput rate ? ? 500 ksps analog inputs input voltage range 0 ? vref v input capacitance ? 5 ? pf temperature sensor ? ? ? linearity 1,2,3 ? 0.5 ? c gain 1,2,3 ? 3350 110 ? v / c offset 1,2,3 (temp = 0 c) ? 89731 ? mv power specifications power supply current ? (v dd supplied to adc0) operating mode, 500 ksps ? 400 900 a power supply rejection ? 0.3 ? mv/v notes: 1. re presents one standard deviation from the mean. 2. measured with pga gain = 2. 3. includes adc offset, gain, and linearity variations. rev. 2.9 47 c8051f300/1/2/3/4/5
c8051f300/1/2/3/4/5 48 rev. 2.9 n otes :
rev. 2.9 49 c8051f300/1/2/3/4/5 6. voltage reference (c8051f300/2) the voltage reference mux on c8051f300/2 devices is configurable to use an externally connected volt - age reference or the power supply voltage, v dd (see figure 6.1 ). the refsl bit in the reference control register (ref0cn) selects the reference source. for an external source, refsl should be set to ?0?; for v dd as the reference source, refsl should be set to ?1?. the biase bit enables th e internal vol t age bi as generator, which is used by the adc, temperature sensor, and internal oscilla tor. this bit is forced to logic 1 when an y of the aforementioned peripherals is enabled. the bias generator may be enabled manually by writing a ?1? to the biase bi t in register ref0cn; see sfr definition 6.1 for ref0cn register details. the electrical sp ecifica tions for the voltage reference cir - cuit are given in ta b l e 6.1 . important note about the vref input: por t pin p0.0 is used as the external vref input. when using an external voltage reference, p0.0 should be configured as analog input and skipped by the digital crossbar. to configure p0.0 as analog input, se t to ?1? bit0 in register p0mdin. to configure the crossbar to skip p0.0, set to ?1? bit0 in register xbr0. refer to section ?12. port input/output? on page 103 for complete port i/o configuration details. the external r e ference voltage must be within the range 0 ? vref ? v dd . on c8051f300/2 devices, the temperature sensor connect s to the highest order i nput of the adc0 positive input multiplexer (see section ?5.1. analog multiplexer and pga? on page 36 for details). the tempe bit in register ref0cn enables/disables the temperat ur e sensor. while disabled, the temperature sensor defaults to a high impedance state and any adc0 measurements performed on the sensor result in mean - ingless data. internal vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd ref0cn refsl tempe biase temp sensor en bias generator to adc, internal oscillator, temperature sensor en ioscen 0 1 figure 6.1. voltage refere nce functional block diagram
c8051f300/1/2/3/4/5 50 rev. 2.9 sfr definition 6.1. bits7?3: unused. read = 00000b; write = don?t care. bit3: refsl: voltage reference select. this bit selects the source for the internal voltage reference. 0: vref input pin used as voltage reference. 1: v dd used as voltage reference. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: internal analog bias generator enable bit. (must be ?1? if using adc). 0: internal bias generator off. 1: internal bias generator on. bit0: unused. read = 0b. write = don?t care. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? refsl tempe biase ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1 ref0cn: reference control register table 6.1. external voltage reference ci rcuit electrical characteristics v dd = 3.0 v; ?40 to +85c unless otherwise specified. parameter conditions min typ max units input voltage range 0 ? v dd v input current sample rate = 500 ksps; vref = 3.0 v ? 12 ? a
rev. 2.9 51 c8051f300/1/2/3/4/5 7. comparator0 c8051f300/1/2/3/4/5 devices include an on-chip prog rammable voltage comparator, which is shown in figure 7.1 . comparator0 offers programmable response time a nd h ysteresis, an analog input multiplexer, and two outputs that are optionally available at the po r t p ins: a synchronous ?latched? output (cp0), or an asynchronous ?raw? output (cp0a) . the asynchronous cp0a signal is available even when the system clock is not active. this allows comparator0 to op erate and generate an output with the device in stop mode. when assigned to a port pin, the comparator0 output may be configured as open drain or push-pull (see section ?12.2. port i/o initialization? on page 106 ). comparator0 may also be used as a reset source (see section ?9.5. comparator0 reset? on page 85 ). the inputs for comparator0 are selected in the cp t0mx re gister (sfr definition 7.2). the cmx0p1- cmx0p0 bits select the comparator0 positive inpu t; th e cmx0n1-cmx0n0 bits select the comparator0 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con - figured as analog inputs in their associated port co nfigur ation register, and configured to be skipped by the crossbar (for details on port configuration, see section ?12.3. general purpose port i/o? on page 108 ). vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + p0.0 p0.2 p0.4 p0.6 cp0 - p0.1 p0.3 p0.5 p0.7 cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n1 cmx0n0 cmx0p1 cmx0p0 cpt0md cp0md1 cp0md0 cp0 rising-edge interrupt flag cp0 falling-edge interrupt flag cp0 cp0a figure 7.1. comparator0 functional block diagram
c8051f300/1/2/3/4/5 52 rev. 2.9 the output of comparator0 can be polled in software, us ed as an interrupt source, and/or routed to a port pin. when routed to a port pin, the comparator0 output is available asynchronous or synchronous to the system clock; the asynchronous output is available ev en in stop mode (with no system clock active). when disabled, the comparator0 output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and its supply current falls to less than 100 na. see section ?12.1. priority crossbar decoder? on page 104 for details on configuring the comparator0 output via the digital crossbar. comparator0 inputs can be externally driven from ?0.25 to (v dd ) + 0.25 v without damage or upset. the comp lete electrical specifications for comparator0 are given in ta b l e 7.1 . the comparator0 response time may be configured in software via the cp0md1-0 bits in register cpt0md (see sfr definition 7.3 ). selecting a longer response time r edu ces the amount of power con - sumed by comparator0. see table 7.1 for complete timing and power consumption specifications. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol figure 7.2. compar ator hysteresis plot the hysteresis of comparator0 is software-programmable via its comparator0 control register (cpt0cn). the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator0 hysteresis is programmed using bi t s 3?0 in the comparator0 control regi ster cpt0cn (shown in sfr definition 7.1 ). the amount of negative hysteresis vo lt ag e is determined by the settings of the cp0hyn bits. as shown in figure 7.2 , settings of 20, 10 or 5 mv of negative hysteresis can be pro - grammed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits.
rev. 2.9 53 c8051f300/1/2/3/4/5 comparator0 interrupts can be gener ated on both rising-edge and falling- edge output transitions. (for interrupt enable and priority control, see section ?8.3. interrupt handler? on page 72 ). the cp0fif flag is set to logic 1 upon a comparator0 falling-edge interrupt, and the cp0rif flag is set to logic 1 upon the com p arator0 rising-edge interrupt. once set, these bits remain set until cleared by software. the output state of comparator0 can be obtained at any time by reading the cp0out bit. comparator0 is enabled by setting the cp0en bit to logic 1, and is di sabled by clearing this bit to logic 0. sfr definition 7.1. bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0?. 1: voltage on cp0+ > cp0?. bit5: cp0rif: comparator0 rising-edge interrupt flag. 0: no comparator0 rising edge interrupt has occurred since this flag was last cleared. 1: comparator0 rising edge interrupt has occurred. bit4: cp0fif: comparator0 fa lling-edge inte rrupt flag. 0: no comparator0 falling-edge interrupt has occurred sinc e this flag was last cleared. 1: comparator0 falling-edge interrupt has occurred. bits3?2: cp0hyp1?0: comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp0hyn1?0: comparator0 nega tive hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf8 cpt0cn: comparator0 control
c8051f300/1/2/3/4/5 54 rev. 2.9 sfr definition 7.2. bits7?6: unused. read = 00b, write = don?t care. bits6?4: cmx0n1?cmx0n0: comparat or0 negative input mux select. these bits select which port pin is us ed as the comparator0 negative input. bits3?2: unused. read = 00b, write = don?t care. bits1?0: cmx0p1?cmx0p0: comparator0 positive input mux select. these bits select which port pin is us ed as the comparator0 positive input. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? cmx0n1 cmx0n0 ? ? cmx0p1 cmx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f cmx0n1 cmx0n0 negative input 00 p0.1 01 p0.3 10 p0.5 11 p0.7 cmx0p1 cmx0p0 positive input 00 p0.0 01 p0.2 10 p0.4 11 p0.6 cpt0mx: comparator0 mux selection sfr definition 7.3. bits7?2: unused. read = 000000b, write = don?t care. bits1?0: cp0md1?cp0md0: comparator0 mode select. these bits select the response time for comparator0. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? cp0md1 cp0md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d mode cp0md1 cp0md0 cp0 response time (typ) 0 0 0 fastest response time 101 ? 210 ? 3 1 1 lowest power consumption cpt0md: comparator 0 mode selection
table 7.1. comparator0 electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units response time: mode 0, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 100 ? ns cp0+ ? cp0? = ?100 mv ? 250 ? ns response time: mode 1, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 175 ? ns cp0+ ? cp0? = ?100 mv ? 500 ? ns response time: mode 2, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 320 ? ns cp0+ ? cp0? = ?100 mv ? 1100 ? ns response time: mode 3, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 1050 ? ns cp0+ ? cp0? = ?100 mv ? 5200 ? ns common-mode rejection ratio ? 1.5 4 mv/v positive hysteresis 1 cp0hyp1?0 = 00 ? 0 1 mv positive hysteresis 2 cp0hyp1?0 = 01 3 5 7 mv positive hysteresis 3 cp0hyp1?0 = 10 7 10 15 mv positive hysteresis 4 cp0hyp1?0 = 11 15 20 25 mv negative hysteresis 1 cp0hyn1?0 = 00 ? 0 1 mv negative hysteresis 2 cp0hyn1?0 = 01 3 5 7 mv negative hysteresis 3 cp0hyn1?0 = 10 7 10 15 mv negative hysteresis 4 cp0hyn1?0 = 11 15 20 25 mv inverting or non-inverting inpu t v oltage range ?0.25 ? v dd + 0.25 v input capacitance ? 7 ? pf input bias current ?5 0.001 +5 na input offset voltage ?5 ? +5 mv power supply power supply rejection ? 0.1 1 mv/v power-up time ? 10 ? s supply current at dc mode 0 ? 7.6 ? a mode 1 ? 3.2 ? a mode 2 ? 1.3 ? a mode 3 ? 0.4 ? a *note: vcm is the common-mode voltage on cp0+ and cp0?. rev. 2.9 55 c8051f300/1/2/3/4/5
c8051f300/1/2/3/4/5 56 rev. 2.9 n otes :
rev. 2.9 57 c8051f300/1/2/3/4/5 8. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft - ware. the mcu family has a superset of all the peripherals included with a standard 8051. included are thr e e 16-bit counter/timers (see description in section 15 ), an enhanced full-duplex uart (see description in section 14 ), 256 bytes of internal ram, 128 byte special function regi ster (sfr) address space ( sec - tion 8.2.6 ), and one byte-wide i/o port (see description in section 12 ). the cip-51 also includes on-chip debug hardware (see description in section 17 ), and interfaces directly with the analog and digital subsys - tems providing a complete data acquisition or contro l-s ystem solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional c u stom peripherals and func tions to extend its capability (see figure 8.1 for a block diagram). the cip-51 includes the following features: data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 figure 8.1. cip-51 block diagram - fully compatible with mcs-51 instruct ion set - extended interrupt handler - 25 mips peak throughput with 25 mhz clock - reset input - 0 to 25 mhz clock frequency - power management modes - 256 bytes of internal ram - on-chip debug logic - byte-wide i/o port - program and data memory security
c8051f300/1/2/3/4/5 58 rev. 2.9 performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core exec ut es 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu - tion time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is ac complished via the silicon labs 2-wire de velopment interface (c2). note that the re-program - mable flash can also be read and changed a single by te at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data stor - age as well as updating program code under software control. the on-chip debug support logic facilit ates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem - ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or ot he r on-chip resources. c2 details can be found in section ?17. c2 interface? on page 173 . the cip-51 is support ed by devel opment tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) includ ing ed itor, macro assembler, debugger and pro - grammer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast a nd e fficient in-system device programming and deb ugging. third party macro assemblers and c compil - ers are also available. 8.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 in str uctions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 8.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most in str uctions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 8.1 is the
rev. 2.9 59 c8051f300/1/2/3/4/5 cip-51 instruct ion set summary , which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 8.1.2. movx instruction and program memory the movx instruction is typically used to access external data memory (note: the c8051f300/1/2/3/4/5 does not support external data or program memory). in the cip-51, the movx instruction accesses the on- chip program memory space implemented as re-programmable flash memory. this feature provides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile data storage. refer to section ?10. flash memory? on page 89 for further details. table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2
c8051f300/1/2/3/4/5 60 rev. 2.9 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 table 8.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
rev. 2.9 61 c8051f300/1/2/3/4/5 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 table 8.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
c8051f300/1/2/3/4/5 62 rev. 2.9 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not eq ua l 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not eq ua l 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location address ed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00- 0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8k-byte program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. table 8.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
rev. 2.9 63 c8051f300/1/2/3/4/5 8.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different in struction types. the cip-51 memory organization is shown in figure 8.2 and figure 8.3 . 8.2.1. program memory the cip-51 core has a 64k-byte program memory spac e. the c8051f300/1/2/3 implements 8192 bytes of this program memory space as in-system, reprogrammable flash me mory, organized in a contiguous block from addresses 0x0000 to 0x1fff. note: 512 by tes (0x1e00 - 0x1fff) of this memory are reserved for factory use and are not available for user progra m storage. the c8051f304 implements 4096 bytes of reprogrammable flash program memory space; the c8051f305 implements 2048 bytes of reprogramma - ble flash program memory space. figure 8.2 shows the program memory maps for c8051f300/1/2/3/4/5 devices. flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x1000 0x0fff c8051f304 (4k flash) c8051f300/1/2/3 (8k flash) flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x1e00 0x1dff flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x0800 0x07ff c8051f305 (2k flash) figure 8.2. program memory maps program memory is normally assumed to be read-only . however, the cip-51 can write to program memory by setting the program store write enable bit (psctl.0) and using the movx instru ction. this feature pro - vides a mechanism for the cip-51 to update program cod e and use the program memory space for non- volatile data storage. refer to section ?10. flash memory? on page 89 for further details.
c8051f300/1/2/3/4/5 64 rev. 2.9 8.2.2. data memory the cip-51 includes 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general pu rp ose registers and scratch pad mem - ory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. loca - tions 0x00 through 0x1f are addressable as four banks of gen er al purpose register s, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as by te s or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndir e ct addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or th e sfrs. in str uctions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 8.3 illustrates the data memory organization of the cip-51. (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space figure 8.3. data memory map 8.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen - eral-purpose registers. each bank consists of eigh t b y te-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 8.4 ). this allows fast context switching when entering subroutines and inte rr upt service routines. indirect addressing modes use registers r0 and r1 as index registers.
rev. 2.9 65 c8051f300/1/2/3/4/5 8.2.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x 00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0 x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alternate no tation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 8.2.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp, 0x81) sfr. the sp will poin t to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 8.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the subsystems unique to the mcu. this allows the addition of new functionality while retain ing compatibility with the mc s-51? instruction set. ta b l e 8.2 list s the sfrs imple - mented in the cip-51 system controller. the sfr registers are accessed anytime the direct ad dr essing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x 0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the datasheet, as indicated in ta b l e 8.3 , for a detailed description of each register.
table 8.2. special function regist er (sfr) memory map c8051f300/1/2/3/4/5 66 rev. 2.9 f8 cpt0cn pca0l pca0h pca0cpl0 pca0cph0 f0 bp0mdin eip1 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 rstsrc e0 acc xbr0 xbr1 xbr2 it01cf eie1 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 d0 psw ref0cn c8 tmr2cn tmr2rll tmr2rlh tmr2l tmr2h c0 smb0cn smb0cf smb0dat adc0gt adc0lt b8 ip amx0sl adc0cf adc0 b0 oscxcn oscicn oscicl flscl flkey a8 ie a0 p0mdout 98 scon0 sbuf0 cpt0md cpt0mx 90 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable) table 8.3. special function registers* register address description page no. acc 0xe0 accumulator 71 adc0cf 0xbc adc0 configuration 43 adc0cn 0xe8 adc0 control 44 adc0gt 0xc4 adc0 greater-than compare word 46 adc0lt 0xc6 adc0 less-than compare word 46 adc0 0xbe adc0 data word 43 amx0sl 0xbb adc0 multiplexer channel select 42 b 0xf0 b register 71 ckcon 0x8e clock control 149 cpt0cn 0xf8 comparator0 control 53 cpt0md 0x9d comparator0 mode selection 54 cpt0mx 0x9f comparator0 mux selection 54 dph 0x83 data pointer high 69 dpl 0x82 data pointer low 68 eie1 0xe6 extended interrupt enable 1 77 eip1 0xf6 external interrupt priority 1 78 flkey 0xb7 flash lock and key 93 *note: sfrs are listed in alphabetical order. all undefined sfr locations are reserved
rev. 2.9 67 c8051f300/1/2/3/4/5 flscl 0xb6 flash scale 93 ie 0xa8 interrupt enable 75 ip 0xb8 interrupt priority 76 it01cf 0xe4 int0/int1 configuration register 79 oscicl 0xb3 internal oscillator calibration 98 oscicn 0xb2 internal oscillator control 98 oscxcn 0xb1 external oscillator control 100 p0 0x80 port 0 latch 109 p0mdin 0xf1 port 0 input mode configuration 109 p0mdout 0xa4 port 0 output mode configuration 110 pca0cn 0xd8 pca control 167 pca0md 0xd9 pca mode 168 pca0cph0 0xfc pca capture 0 high 171 pca0cph1 0xea pca capture 1 high 171 pca0cph2 0xec pca capture 2 high 171 pca0cpl0 0xfb pca capture 0 low 171 pca0cpl1 0xe9 pca capture 1 low 171 pca0cpl2 0xeb pca capture 2 low 171 pca0cpm0 0xda pca module 0 mode register 169 pca0cpm1 0xdb pca module 1 mode register 169 pca0cpm2 0xdc pca module 2 mode register 169 pca0h 0xfa pca counter high 170 pca0l 0xf9 pca counter low 170 pcon 0x87 power control 81 psctl 0x8f program store r/w control 92 psw 0xd0 program status word 70 ref0cn 0xd1 voltage reference control 49 rstsrc 0xef reset source configuration/status 87 sbuf0 0x99 uart 0 data buffer 137 scon0 0x98 uart 0 control 136 smb0cf 0xc1 smbus configuration 118 smb0cn 0xc0 smbus control 120 smb0dat 0xc2 smbus data 122 sp 0x81 stack pointer 69 tmr2cn 0xc8 timer/counter 2 control 154 tcon 0x88 timer/counter control 147 th0 0x8c timer/counter 0 high 150 table 8.3. special function registers* (continued) register address description page no. *note: sfrs are listed in alphabetical order. all undefined sfr locations are reserved
c8051f300/1/2/3/4/5 68 rev. 2.9 8.2.7. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default st ate. det ailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding sys - tem function. sfr definition 8.1. bits7?0: dpl: data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 dpl: data pointer low byte th1 0x8d timer/counter 1 high 150 tl0 0x8a timer/counter 0 low 150 tl1 0x8b timer/counter 1 low 150 tmod 0x89 timer/counter mode 148 tmr2rlh 0xcb timer/counter 2 reload high 154 tmr2rll 0xca timer/counter 2 reload low 154 tmr2h 0xcd timer/counter 2 high 154 tmr2l 0xcc timer/counter 2 low 154 xbr0 0xe1 port i/o crossbar control 0 107 xbr1 0xe2 port i/o crossbar control 1 107 xbr2 0xe3 port i/o crossbar control 2 108 0x97, 0xae, 0xaf, 0xb4, 0 x b6, 0xbf, 0xce, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xdd, 0xde, 0xdf, 0xf5 reserved table 8.3. special function registers* (continued) register address description page no. *note: sfrs are listed in alphabetical order. all undefined sfr locations are reserved
rev. 2.9 69 c8051f300/1/2/3/4/5 sfr definition 8.2. bits7?0: dph: data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0x83 dph: data pointer high byte sfr definition 8.3. bits7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp r egister defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81 sp: stack pointer
c8051f300/1/2/3/4/5 70 rev. 2.9 sfr definition 8.4. bit7: cy: carry flag. this bit is set when the last arithmetic operat ion resulted in a carry (addition) or a borrow (subtraction). it is cleared to logi c 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operati on resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arithmetic opera- tions. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4?3: rs1-rs0: register bank select. these bits select which register ban k is used during register accesses. ? bit2: ov: overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instructio n causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div instructions in all other cases. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. this bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. r/w r/w r/w r/w r/w r/w r/w r reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd0 rs1 rs0 register bank address 0 0 0 0x00?0x07 0 1 1 0x08?0x0f 1 0 2 0x10?0x17 1 1 3 0x18?0x1f psw: program status word
rev. 2.9 71 c8051f300/1/2/3/4/5 sfr definition 8.5. bits7?0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc. 3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe0 acc: accumulator sfr definition 8.6. bits7?0: b: b register. this register serves as a second accumu lator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf0 b: b register
c8051f300/1/2/3/4/5 72 rev. 2.9 8.3. interrupt handler the cip-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two prior - ity levels. the allocation of inter rupt sources between on-chip periph erals and external inputs pins varies according to the specific version of the device. each interrupt source has one or more associated interrupt- pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt-pend ing flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt se rvice ro utine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal . (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or di sabled through the use of an associated interrupt enable bit in an sfr (ie-eie1). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are re cogn ized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears the ea bit should be immediately followed by an instruction that has two or more opcode bytes. for example: // in 'c': ? ea = 0; // clear ea bit ? ea = 0; // ... followed by another 2-byte opcode ? ? ; in assembly: ? clr ea ; clear ea bit ? clr ea ; ... followed by another 2-byte opcode if an interrupt is posted during the execution phase of a "clr ea" opcode (or an y instruction which clears the ea bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. how - ever, a read of the ea bit will return a '0' inside the inte rrupt service routin e. when the "clr ea" opcode is followed by a multi-cycle instruct ion, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interrupt request will be generat ed immediately and the cpu will reenter the isr after the completion of th e next instruction. 8.3.1. mcu interrupt sources and vectors the mcus support 12 interrupt sources. software can simulate an interrupt by setting any interrupt-pend - ing flag to logic 1. if interrupts are enab led for the flag, an in terrupt reque st will be generat ed and the cpu will vector to the isr address associated with the interrup t-pending flag. mcu inte rrupt sources, associ - ated vector addresses, priority order and control bits are summarized in ta b l e 8.4 on page 74 . refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt co nditions for the peripheral and the behavior of its interrupt-pending flag(s).
rev. 2.9 73 c8051f300/1/2/3/4/5 8.3.2. external interrupts the /int0 and /int1 external interrupt sources are configurable as active high or low, edge or level sensi - tive. the in0pl (/int0 polarity) and in1pl (/int1 polarity ) bit s in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?15.1. timer 0 and timer 1? on page 143 ) select level or edge sensitive. the table below list s the possible configurations. it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 1 0 active low, edge sensitive active low, edge sensitive 1 1 active high, edge sensitive active high, edge sensitive 0 0 active low, level sensitive active low, level sensitive 0 1 active high, level sensitive active high, level sensitive /int0 and /int1 are assigned to port pins as defin ed in the it01cf register (s ee sfr definition 8.11). note that /int0 and /int0 port pin assignments are in dep endent of any crossbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing th e peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int 0 and/or /int1, configure the crossbar to skip the selected pin(s). this is accomplished by setti ng the associated bit in register xbr0 (see section ?12.1. priority crossbar decoder? on page 104 for complete details on c o nfiguring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interr upt- pen ding flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corre - sponding interrupt-pending flag is automatically clear ed by th e hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pendi ng flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in 1pl); the flag remains logi c 0 while the input is inac - tive. the external interrupt source must hold the input a c tive until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. 8.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted b y a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in ta b l e 8.4 . 8.3.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. if a n interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cyc les to complete the div instruction and 4 clock cycles to execute the lcall to the isr. if the cpu is ex ec uting an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. 10 11 00 01
table 8.4. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none always enabled always highe st ext ernal interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) et2 (ie.5) pt2 (ip.5) smbus interface 0x0033 6 si (smb0cn.0) esmb0 (eie1.0) psmb0 (eip1.0) adc0 window compare 0x003b 7 ad0wint (a dc0cn.3) ew adc0 (eie1.1) pwadc0 (eip1.1) adc0 conversion com - plete 0x0043 8 ad0int (a dc0cn.5) eadc0c (eie1.2) pa dc0c (eip1.2) programmable counter array 0x004b 9 cf (pca0cn.7) ccfn (p ca0cn.n) epca0 (eie1.3) ppca0 (eip1.3) comp arator0 falling edge 0x0053 10 cp0fif (c pt 0cn.4) ecp0f (eie1.4) pcp0f (eip1.4) comparator0 rising edge 0x005b 11 cp0rif (c pt 0cn.5) ecp0r (eie1.5) pcp0r (eip1.5) c8051f300/1/2/3/4/5 74 rev. 2.9 n/a n/a yy yy yy yy yn yn yn yn yn yn nn nn
rev. 2.9 75 c8051f300/1/2/3/4/5 8.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). sfr definition 8.7. bit7: ea: enable all interrupts. this bit globally enables/disabl es all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt accord ing to its individual mask setting. bit6: iegf0: general purpose flag 0. this is a general purpose flag for use under software control. bit5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua rt0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti mer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit2: ex1: enable exte rnal interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti mer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit0: ex0: enable exte rnal interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea iegf0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa8 ie: interrupt enable
c8051f300/1/2/3/4/5 76 rev. 2.9 sfr definition 8.8. bits7?6: unused. read = 11b, write = don't care. bit5: pt2: timer 2 interr upt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupts se t to low priority level. 1: timer 2 interrupts set to high priority level. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupts set to low priority level. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interr upt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupts se t to low priority level. 1: timer 1 interrupts set to high priority level. bit2: px1: external interr upt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interr upt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupts se t to low priority level. 1: timer 0 interrupts set to high priority level. bit0: px0: external interr upt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? pt2 ps0 pt1 px1 pt0 px0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb8 ip: interrupt priority
rev. 2.9 77 c8051f300/1/2/3/4/5 sfr definition 8.9. bits7?6: unused. read = 00b. write = don?t care. bit5: ecp0r: enable comparator0 (cp0) rising edge interrupt. this bit sets the masking of the cp0 rising edge interrupt. 0: disable cp0 risin g edge interrupt. 1: enable interrupt requests generated by the cp0rif flag. bit4: ecp0f: enable comparator 0 (cp0) falling edge interrupt. this bit sets the masking of the cp0 falling edge interrupt. 0: disable cp0 falli ng edge interrupt. 1: enable interrupt requests generated by the cp0fif flag. bit3: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. bit2: eadc0c: enable adc0 co nversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conver sion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. bit1: ewadc0: enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag. bit0: esmb0: enable smbus interrupt. this bit sets the masking of the smbus interrupt. 0: disable all smbus interrupts. 1: enable interrupt requests generated by the si flag. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ecp0r ecp0f epca0 eadc0c ewadc0 esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6 eie1: extended interrupt enable 1
c8051f300/1/2/3/4/5 78 rev. 2.9 sfr definition 8.10. bits7?6: unused. read = 11b. write = don?t care. bit5: pcp0r: comparator0 (cp0) ris ing interrupt priority control. this bit sets the priority of the cp0 rising-edge interrupt. 0: cp0 rising interrupt se t to low priority level. 1: cp0 rising interrupt se t to high priority level. bit4: pcp0f: comparator0 (cp0) fa lling interrupt pr iority control. this bit sets the priority of the cp0 falling-edge interrupt. 0: cp0 falling interrupt se t to low priority level. 1: cp0 falling interrupt se t to high priority level. bit3: ppca0: programmable counter arra y (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit2: padc0c adc0 conversion comp lete interrupt pr iority control this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete inte rrupt set to high priority level. bit1: pwadc0: adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. bit0: psmb0: smbus interr upt priority control. this bit sets the priority of the smbus interrupt. 0: smbus interr upt set to low priority level. 1: smbus interrup t set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? pcp0r pcp0f ppca0 padc0c pwadc0 psmb0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6 eip1: extended interrupt priority 1
rev. 2.9 79 c8051f300/1/2/3/4/5 sfr definition 8.11. bit7: in1pl: /int1 polarity 0: /int1 input is active low. 1: /int1 input is active high. bits6?4: in1sl2?0: /int1 port pin selection bits these bits select which port pin is assigned to /int1. note that this pin assignment is inde- pendent of the crossbar; /int1 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register xbr0). bit3: in0pl: /int0 polarity 0: /int0 interrupt is active low. 1: /int0 interrupt is active high. bits2?0: int0sl2?0: /int0 port pin selection bits these bits select which port pin is assigned to /int0. note that this pin assignment is inde- pendent of the crossbar. /int 0 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register xbr0). r/w r/w r/w r/w r/w r/w r/w r/w reset value in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 note: refer to sfr definition 15.1 for int0/1 edge- or level-sensitive interrupt selection. in1sl2?0 /int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2?0 /int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 it01cf: int0/int1 configuration
c8051f300/1/2/3/4/5 80 rev. 2.9 8.4. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all inter - rupts and timers (except the missing clock detector) ar e in active, and the system clock is stopped (analog peripherals remain in their selected states). since cl ocks are running in idle mode, power consumption is dependent upon t he system clock frequency and t he number of peripherals left in active mode before entering idle. stop mode consumes the least power. sfr definition 8.12 describes the power control reg - ister (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in ( as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw littl e power when they are not in use. turning off the oscil - lators lowers power consumption considerably; however a reset is required to restart the mcu. 8.4.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event o f an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro - vides the opportunity for additional power savings, allo w ing the system to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. refer to section ?16.3. watchdog timer mode? on page 164 for more information on the use and configuration of the wdt. note: any instruction that sets the idle bit should be immediately followed by an instruction that ha s 2 or more opcode bytes. for example: // in 'c': pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if the instruction following the write of th e idle bit is a single-byte instruct ion and an interrupt occurs during the execution phase of the instructio n that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs.
rev. 2.9 81 c8051f300/1/2/3/4/5 8.4.2. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc - tion that sets the bit completes exec ution. in s top mode the internal oscillator, cpu, and all digital periph - erals are stopped; the state of the external oscilla tor circ uit is not af fect ed. each analog peripheral (including the external oscillator circui t) may be shut down i ndividually prior to ente ring stop mode. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 sec. sfr definition 8.12. bits7?2: gf5?gf0: general purpose flags 5-0. these are general purpose flags for use under software control. bit1: stop: stop mode select. setting this bit will place the cip-51 in stop mode. this bit will always be read as 0. 1: cpu goes into stop mode (t urns off intern al oscillator). bit0: idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode (s huts off clock to cpu, but cloc k to timers, interrupts, serial ports, and analog peripherals are still active). r/w r/w r/w r/w r/w r/w r/w r/w reset value gf5 gf4 gf3 gf2 gf1 gf0 stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87 pcon: power control
c8051f300/1/2/3/4/5 82 rev. 2.9 n otes :
rev. 2.9 83 c8051f300/1/2/3/4/5 9. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal d a ta memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is re set, and the system clock defaults to the inter - nal oscillator. refer to section ?11. oscillators? on page 97 for information on selecting and configuring the system clock source. the watchdog timer is enabled with the system clock divide d by 12 as its clock source ( section ?16.3. watchdog timer mode? on page 164 details the use of the watchdog timer). once the system clock source is st able, program execution begins at location 0x0000. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel p0.x p0.y en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable xtal1 xtal2 external oscillator drive illegal flash operation + - comparator 0 c0rsef /rst (wired-or) power on reset + - vdd supply monitor enable '0' figure 9.1. reset sources
c8051f300/1/2/3/4/5 84 rev. 2.9 9.1. power-on reset during powerup, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . an additional delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). for valid ramp times (less than 1 ms), the power-on reset delay (t pordelay ) is typically less than 0.3 ms. note: the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the vrst level. on exit from a power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a powerup was the cause of reset. the content of internal data mem - ory should be assumed to be undefined after a power-on reset. the v dd monitor is disabled following a power-on reset. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd figure 9.2. power-on and v dd monitor reset timing 9.2. power-fail reset/v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 9.2 ). when v dd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is disabled after power-on resets; however it s defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is enabled and a software reset is performed, the v dd monitor will still be enabled after the reset. the v dd monitor is enabled by wr iting a ?1? to the porsf
rev. 2.9 85 c8051f300/1/2/3/4/5 bit in register rstsrc. see figure 9.2 for v dd monitor timing; note that the reset delay is not incurred after a v dd monitor reset. see table 9.2 for electrical characteristics of the v dd monitor. important note: ena bling the v dd monitor will immediately generate a system reset. the device will then return from the reset state with the v dd monitor enabled. writing a logic ?1? to the porsf flag when the v dd monitor is enabled does not cause a system reset. 9.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 9.2 for complete rst pin spec - ifications. the pinrsf flag (rstsrc.0) is se t on exit from an external reset. 9.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than 100 s, the one-shot will time out an d generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset. 9.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0?), the device is put into the reset state. afte r a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. 9.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?16.3. watchdog timer mode? on page 164 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is gen erated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset.
c8051f300/1/2/3/4/5 86 rev. 2.9 9.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx o peration is attempted above the user code space address limit. ? a flash read is attempted above user code space. th is occurs when a movc operation is attempted above the user code space address limit. ? a program read is attempted above user code spac e. this occu rs wh en user code attempts to branch to an address above the user code space address limit. table 9.1. user code space address limits device user code space address limit the ferror bit (rstsrc.6) is set following a fla sh error reset. the state of the rst pin is unaffected by this reset. 9.8. software reset software may force a reset by writing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset. table 9.2. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.7 v to 3.6 v ? ? 0.6 v rst input high voltage 0.7 x v dd ? ? v rst input low voltage ? ? 0.3 x v dd rst input leakage current rst = 0.0 v ? 25 40 a v dd monitor threshold (v rst ) 2.40 2.55 2.70 v missing clock detector timeout time from last system clock ris - ing edge to reset initiation 100 220 500 s reset time delay delay between release of any r e set source and code execution at location 0x0000 5.0 ? ? s minimum rst low time to generate a system reset 15 ? ? s v dd ramp time v dd = 0 to v rst ? ? 1 ms c8051f300/1/2/3 0x1dff c8 05 1f304 0x0fff c8051f305 0x07ff
rev. 2.9 87 c8051f300/1/2/3/4/5 sfr definition 9.1. (note: do not use read-modify-write operations (orl, anl) on this register) bit7: unused. read = 0. write = don?t care. bit6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: c0rsef: comparator0 reset enable and flag. write 0: comparator0 is not a reset source. 1: comparator0 is a reset source (active-low). read 0: source of last reset was not comparator0. 1: source of last reset was comparator0. bit4: swrsf: software reset force and flag. write 0: no effect. 1: forces a system reset. read 0: source of last reset was not a write to the swrsf bit. 1: source of last was a write to the swrsf bit. bit3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit2: mcdrsf: missing clock detector flag. write: 0: missing clock detector disabled. 1: missing clock detector enabled; triggers a rese t if a missing clock condition is detected. read: 0: source of last re set was not a missing clock detector timeout. 1: source of last reset was a missing clock detector timeout. bit1: porsf: power-on reset force and flag. this bit is set anytime a power-on reset occurs. this may be due to a true power-on reset or a v dd monitor reset. in either case, data memo ry should be considered indeterminate fol- lowing the reset. writing this bit enables/disables the v dd monitor. write: 0: v dd monitor disabled. 1: v dd monitor enabled. read: 0: last reset was not a power-on or v dd monitor reset. 1: last reset was a power-on or v dd monitor reset; all other reset flags indeterminate. bit0: pinrsf: hw pin reset flag. 0: source of last reset was not rst pin. 1: source of la st reset was rst pin. r r r/w r/w r r/w r/w r reset value ? ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef rstsrc: reset source
c8051f300/1/2/3/4/5 88 rev. 2.9 n otes :
rev. 2.9 89 c8051f300/1/2/3/4/5 10. flash memory on-chip, reprogrammable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system, a single by te at a time, through the c2 interface or by soft - ware using the movx instruction. once cleared to logic 0, a f lash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for pr oper execution; data pollin g to determine the end of the write/erase operation is not required. code execut ion is stalled during a flash write/erase operation. refer to ta b l e 10.1 for complete flash memory e lectrical characteristics. 10.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial - ized device. for details on the c2 commands to program flash memory, see section ?17. c2 interface? on page 173 . to ensure the integrity of flash contents, it is strongly recommended that the on-chip v dd monitor be enabled in any system that includes code that writes and/or erases flash memory from soft - ware. 10.1.1. flash lock and key functions flash writes and erases by user software are protecte d with a lock and key function; flash reads by user software are unrestricted. the flas h lock and key register (flkey) must be written with the correct key codes, in sequence, before flash operations may be performed. the key codes are: 0xa5, 0xf1. the tim - ing does not matter, but the codes must be written in order. if the key codes are written out of order, or the wrong codes are written, flash writes and erases will be disabled until th e next system reset. flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes have been writ - ten properly. the flash lock resets after each write or erase; the key codes must be written again before a following flash operation can be performed. the flkey register is detailed in sfr definition 10.2 . 10.1.2. flash erase procedure the flash memory can be programmed by software using the movx instruction with the address and data byte to be programmed provided as normal operands. before writing to flash memory using movx, flash write operations must be enabled by: (1) setting t he pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flas h memory); and (2) writing the flash key codes in sequence to the flash lo ck register (flkey). the pswe bit rema ins set until cleared by software. a write to flash memory can clear bits but cannot set the m; only an erase operation can set bits in flash. a byte location to be programmed should be erased before a new value is written. the 8k byte flash me mory is organized in 512-byte pages. the erase operat ion applies to an entire page (setting all bytes in the page to 0xff). to erase an entire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). s tep 2. set the program store erase en able bit (psee in the psctl register). step 3. set the program store write enable bit (pswe in the psctl register). step 4. write the first key code to flkey: 0xa5. step 5. write the second key code to flkey: 0xf1. step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased.
c8051f300/1/2/3/4/5 90 rev. 2.9 10.1.3. flash write procedure flash bytes are programmed by software with the following sequence: step 1. disable interrupts (recommended). s t ep 2. erase the 512-byte flash page containing the target location, as described in section 10.1.2 . step 3. set the pswe bit in psctl. step 4. clear the psee bit in psctl. step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write a single data byte to the desired location within the 512- byte sector. steps 5?7 must be repeated for each byte to be written. after flash writes are complete, pswe should be clea re d so that movx instructions do not target program memory. writing to and erasing the reserved area of flash should be avoided. table 10.1. flash electrical characteristics flash size c8051f300/1/2/3 8192* bytes c8051f304 4096 bytes c8051f305 2048 bytes endurance 20k 100k erase/write erase cycle time 25 mhz system clock 10 15 20 ms write cycle time 25 mhz system clock 40 55 70 s sysclk frequency (flash writes from application code) 10 0 khz *note: 512 bytes at location 0x1e00 to 0x1fff are reserved. 10.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx instruction and read using the movc instruction. 10.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store w r ite enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte stored at the last byte of flas h use r space protects the flash program memory from being read or altered across the c2 interface. see ta b l e 10.2 for the security by te descript i on; see figure 10.1 for a program memory map and the security byte locations for each device. parameter conditions min typ max units
table 10.2. security byte decoding bits description write lock: cle aring any of these bits to logic 0 prevents all flash memory from being written or page-erased across the c2 interface read/write lock: cle aring any of these bits to logic 0 prevents all flash memory from being read, written, or page-erased across the c2 interface. rev. 2.9 91 c8051f300/1/2/3/4/5 the lock bits can always be read and cleared to logic 0 regardless of the security settings. important note: the only means of removing a lock (write or read/write) once set is to erase the entire program memory space via a c2 device erase command. c8051f300/1/2/3 0x0000 0x1dff lock byte reserved 0x1dfe flash memory organized in 512-byte pages 0x1e00 0x0000 0x0fff reserved 0x0ffe flash memory organized in 512-byte pages 0x1000 0x0000 0x07ff lock byte reserved 0x07fe flash memory organized in 512-byte pages 0x0800 lock byte c8051f304 c8051f305 figure 10.1. flash program memory map the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. accessing flash f r om the c2 debug interface : 1. any unlocked page may be read, written, or erased. 2. locked pages cannot be read, written, or erased. 3. the page containing the lock byte may be read , written, or eras ed if it is unlocked. 4. reading the contents of the lock byte is always p e rmitted only if no pages are locked. 5. locking additional pages (changing ?1?s to ?0? s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0 ? s to ?1?s in the lock byte) requires the c2 device erase com - mand, which erases all flash pages including t he p age containing the lock byte and the lock byte itself. 7. the reserved area cannot be read, written, or erased. 7?4 3?0
c8051f300/1/2/3/4/5 92 rev. 2.9 accessing flash from user firmware executing from an unlocked page : 1. any unlocked page except the page containing th e lock byte may be read, written, or erased. 2. locked pages cannot be read, written, or erased. an erase attempt on the page containing the lock byte will result in a flash error device reset. 3. th e page containing the lock byte cannot be erased. it m ay be read or written only if it is unlocked. an erase attempt on the page containing the lock byte will result in a flash error device reset. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0? s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1? s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will result in a flash error device reset. accessing flash f rom use r firmware executing from a locked page : 1. any unlocked page except the page containing th e lo ck byte ma y be read, written, or erased. 2. any locked page except the page containing the lo ck byte may be read, written, or erased. an erase attempt on the page cont aining the lock byte will result in a flash error device reset. 3. th e page containing the lock byte cannot be erased. it may only be read or written. an erase attempt on the page containing the lock byte will result in a flash error device reset. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing ?1?s to ?0? s in the lock byte) is not permitted. 6. unlocking flash pages (changing ?0?s to ?1? s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will result in a flash error device reset. sfr definition 10.1. bits7?2: unused: read = 000000b, write = don?t care. bit1: psee: program store erase enable setting this bit (in combination with pswe) a llows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx in struction will erase the entire page that contains the loca- tion addressed by the movx instruction. the va lue of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx instruction. the flash location sh ould be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx instruction targets flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f psctl: program store r/w control
rev. 2.9 93 c8051f300/1/2/3/4/5 sfr definition 10.2. bits7?0: flkey: flash lock and key register write: this register must be writte n to before flash writes or erases can be performed. flash remains locked until this regist er is written to with the following key codes: 0xa5, 0xf1. the timing of the writes does not matter, as long as the codes are written in order. the key codes must be written for each flas h write or erase operation. fl ash will be locked until the next system reset if the wrong codes are written or if a flash operation is attempted before the codes have been written correctly. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (w rites/erases allowed). 11: flash writes/erases disa bled until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7 flkey: flash lock and key sfr definition 10.3. bits7: fose: flash one-shot enable this bit enables the 50 ns flash read one-sh ot. when the flash o ne-shot disabled, the flash sense amps are enabled for a full clock cycle during flash reads. 0: flash one-shot disabled. 1: flash one-shot enabled. bits6?0: reserved. read = 0. must write 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value fose reserved reserved reserved reserved reserved reserved reserved 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6 flscl: flash scale
c8051f300/1/2/3/4/5 94 rev. 2.9 10.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of v dd , system clock frequency, or temperature. this accidental execution of flash modi - fying code can result in alteration of flash memory conte nts causing a system failure that is only recover - able by re-flashing the code in the device. the following guidelines are recommended f or any syst em which contains routin es which write or erase flash from code. 10.4.1. v dd maintenance and the v dd monitor 1. if the system power supply is subject to volta ge or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum v dd rise time specification of 1 ms is met. if the system cannot meet this rise time specification, then add an external v dd brownout circuit to the rst pin of the device that holds the device in reset until v dd reaches 2.7 v and re-asserts rst if v dd drops below 2.7 v. 3. enable the on-chip v dd monitor and enable the v dd monitor as a reset source as early in code as possible. this should be the first set of inst ructions executed after the reset vector. for 'c'- based systems, this will involve modifying the st artup code added by the 'c' compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the v dd monitor and enabling the v dd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware", available from the silicon laboratories web site. 4. as an added precaution, explicitly enable the v dd monitor and enable the v dd monitor as a reset source inside the functions that write and erase flash memory. the v dd monitor enable instructions should be placed just after the in struction to set pswe to a '1', but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (r eset sour ces) register use direct assignment operators and explicitly do not use the bit- wise operators (such as and or or). for exam - ple, "rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regist e r explicitly set the porsf bit to a '1'. areas to check are initialization code which enables ot her reset sources, such as the missing clock detector or comparator, for example, and instru ctions which force a so ftware reset. a global search on "rstsrc" can quickly verify this. 10.4.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a '1'. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one rou - tine in code that sets pswe and psee bo th to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a '1'. handle pointer address updates and loop variable maintenance outside the "pswe = 1; ... pswe = 0;" area. code examples showing this can be found in an201, "writing to flash from firmware" , available from the silicon laboratories web site. 9. disable interrupts prior to setti ng pswe to a '1' and leave them disabled until after pswe has been reset to '0'. any interrup ts posted during the flash writ e or erase operation will be ser -
rev. 2.9 95 c8051f300/1/2/3/4/5 viced in priority order after the flash operation has been completed and interrupts have been re-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see your compiler documentation for instructions regard ing how to explicitly lo cate variables in dif - ferent memory areas. 11. add address bounds checking to the routines th at write or erase flash memory to ensure that a routine called with an illegal address does not re sult in modification of the flash. 10.4.3. system clock 12. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noi sy environment, use the internal oscillator or use an external cmos clock. 13. if operating from the ex ternal osc illator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after th e flash operation has completed. additional flash recommendations and example code can be found in an2 01, "writing to flash from firm - ware" , available from the silic on laboratories web site.
c8051f300/1/2/3/4/5 96 rev. 2.9 n otes :
rev. 2.9 97 c8051f300/1/2/3/4/5 11. oscillators c8051f300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive circuit. the internal oscillator ca n be enabled/disabled and calibrated using the oscicn and oscicl reg - isters, as shown in figure 11.1 . the system clock can be sourced by the ex ternal os cillator circuit, the internal oscillator, or a scaled versio n of the internal oscillator . the inte rnal oscillator's electrical specifica - tions are given in ta b l e 11.1 on page 99 . osc programmable internal clock generator input circuit en sysclk n oscicl oscicn ifrdy clksl ioscen ifcn1 ifcn0 xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 figure 11.1. oscillator diagram 11.1. programmable in te rnal oscillator all c8051f300/1/2/3/4/5 de vices include a programmabl e internal oscillator that defaults as the system clock after a system reset. the internal oscillator period can be ad justed via the oscicl register as defined by sfr definition 11.1 . on c8051f300/1 devices, oscicl is fact ory calibrated to obt ain a 24.5 mhz frequency. on c 8051f302/3/4/5 devic e s, the osc illator frequency is a nominal 20 mhz and may vary 20% from device-to-device. electrical specifications fo r th e pre cision internal oscillator are given in table 11.1 on page 99. the pro - grammed internal o scillator frequency mu s t not exceed 25 mhz. note that the system clock may be deriv ed from the programmed in ternal oscillator divided by 1, 2, 4, or 8, as define d by the ifcn bits in reg - ister oscicn. the divide value def ault s to 8 following a reset.
c8051f300/1/2/3/4/5 98 rev. 2.9 sfr definition 11.1. bit7: unused. read = 0. write = don?t care. bits 6?0: oscicl: internal os cillator calibration register. this register calibrates the internal oscillator period. the reset value for oscicl defines the internal oscillator base frequency. on c8051f300/1 devices, the reset value is factory cali- brated to generate an internal oscillator fre quency of 24.5 mhz. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb3 oscicl: internal osci llator calibration sfr definition 11.2. bits7?5: unused. read = 000b, write = don't care. bit4: ifrdy: internal oscilla tor frequency ready flag. 0: internal oscillator is not running at prog rammed frequency. 1: internal oscillator is r unning at progra mmed frequency. bit3: clksl: system clo ck source select bit. 0: sysclk derived from the internal oscillator, and sc aled as per the ifcn bits. 1: sysclk derived from the external oscillator circuit. bit2: ioscen: internal oscillator enable bit. 0: internal osc illator disabled. 1: internal oscillator enabled. bits1?0: ifcn1-0: internal osc illator frequency control bits. 00: sysclk derived from intern al oscillator divided by 8. 01: sysclk derived from intern al oscillator divided by 4. 10: sysclk derived from intern al oscillator divided by 2. 11: sysclk derived from internal oscillator divided by 1. r/w r/w r/w r r/w r/w r/w r/w reset value ? ? ? ifrdy clksl ioscen ifcn1 ifcn0 00010100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2 oscicn: internal o scillator control
table 11.1. internal oscillator elec trical cha racteristics ?40 to +85 c unless otherwise specified calibrated internal oscillator frequency c8051f300/1 devices ?40 to +85 c 24 24.5 25 mhz c8051f300/1 devices 0 to +70 c 24.3 24.7 25 mhz uncalibrated internal oscillator f r equency c8051f302/3/4/5 devices 16 20 24 mhz internal oscillato r supply current (f rom v dd ) oscicn.2 = 1 450 a 11.2. external oscillator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys - tal/resonator must be wired across the xtal1 and xtal2 pins as shown in option 1 of figure 11.1 . a 10 m ?? r esistor also must be wired across the xtal2 an d xtal1 pins for the crystal/resonator configura - tion. in rc, capacitor, or cmos cl o c k configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 11.1 . the type of external oscillator mus t be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 11.3 ). important note on external oscillator usage: po rt pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/resonator mode, port pins p0.2 and p0.3 are occupied as xtal 1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is occupied as xtal2. the port i/o cross - bar should be configured to skip the occupie d port pins; see section ?12.1. priority crossbar decoder? on page 104 for crossbar configuration. additionally , when using the exte rnal oscillator circuit in crys - tal/resonator, capacitor, or rc mode, the associated port pins should be configured as ana l og inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?12.2. port i/o initialization? on page 106 for details on port input mode selec tion. 11.3. system clock selection the clksl bit in register oscicn selects which oscilla tor is used as the system clock. clksl must be set to ?1? for the system clock to run from the external oscillator; ho wever the external oscillator may still clock peripherals (timers, pca) when the internal oscillator is selected as the system clock. the system clock may be switched on -the-fly betwe en the internal and exter nal oscillator, so long as the selected oscil - lator is enabled and has settled. the internal oscilla tor requires little s t art-up ti me and may be enabled and selected as the system clock in the same write to oscicn. external crystals and ceramic resonators typi - cally require a start-up time before they are settled and rea dy for use as the system clock. the crystal valid flag (xtlvld in register oscxcn ) is set to ?1? by hardware when t he external oscillator is settled. to avoid reading a false xtlvld, in crystal mode software should delay at least 1 ms between enabling the ex ternal oscillator and checking xtlvld. rc and c modes typically require no start-up time. rev. 2.9 99 c8051f300/1/2/3/4/5 parameter conditions min typ max units
c8051f300/1/2/3/4/5 100 rev. 2.9 sfr definition 11.3. oscxcn: external o scillator control bit7: xtlvld: crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits6?4: xoscmd2-0: extern al oscillator mode bits. 00x: external osc illator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode with divide by 2 stage. 101: capacitor oscillator mode with divide by 2 stage. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = 0, write = don't care. bits2?0: xfcn2-0: external osc illator frequency control bits. 000-111: see table below: crystal mode (circuit from figure 11.1 , option 1; xoscmd = 11x) choose xfcn value to match crystal frequency. rc mode (circuit from figure 11.1 , option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 ) / (r x c) , where f = frequency of oscillation in mhz c = capacitor value in pf r = pull-up resist or value in k ? c mode (circuit from figure 11.1, option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf / (c x v dd ) , where f = frequency of oscillation in mhz c = capacitor value the xtal2 pin in pf v dd = power supply on mcu in volts r r/w r/w r/w r r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd 0 ? xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb1 xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590 khz 100 khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590
rev. 2.9 101 c8051f300/1/2/3/4/5 11.4. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 11.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the table in sfr definition 11.3 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is first e nabled, the oscillator amplitude detecti on circuit requires a settling time to achieve proper bias. introducing a delay of 1 ms between enabling the o scillator and c hecking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec - ommended procedure is: step 1. force the xtal1 and xtal2 pins low by writing 0?s to the port latch. s tep 2. configure xtal1 and xtal2 as analog inputs. step 3. enable the external oscillator. step 4. wait at least 1 ms. step 5. poll for xtlvld => ?1?. step 6. switch the system cl ock to the external oscillator. note: tuning-fork crystals may require additional settling time before xtlvld returns a valid result. the capacitors shown in the external crystal configur atio n provide the load capacitance required by the crystal for correct oscillation. these capacitors are ?in series? as seen by the crystal and ?in parallel? with the stray capacitance of the xtal1 and xtal2 pins. note: the load capacitance depends upon the crystal and the manufacturer. please refer to the c rystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should u se the configuration shown in figure 12.1, option 1. the total value of the capacitors and the stray capac - itance of the xtal pins should equal 25 pf. with a stray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 11.2 . figure 11.2. 32.768 khz external crystal example 22 pf 22 pf 32.768 khz 10 m xtal1 xtal2 ?
c8051f300/1/2/3/4/5 102 rev. 2.9 11.5. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 11.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion. if the frequency desired is 100 khz, let r = 246 k? an d c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 11.3, the required xfcn setting is 010b. 11.6. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 11.1 , option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c ca pacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci - tor to be used and find the fr equenc y of oscillati on from the equations below. assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, select the k factor fr om the table in sfr definition 11.3 as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf.
gnd /port-outenable port-output push-pull vdd vdd /weak-pullup (weak) port pad analog input analog select port-input rev. 2.9 103 c8051f300/1/2/3/4/5 12. port input/output digital and analog resources are available through a byte-wide digital i/o port, port0. each of the port pins can be defined as general-purpose i/o (gpio), analog input, or assigned to one of the internal digital resources as shown in figure 12.3 . the designer has complete control over which functions are assigned, limited only by the number of physic al i/o pins. this resour ce assignment flexibility is achieved through the use of a priority crossbar decoder. note that the stat e of a port i/o pin can always be read in the corre - sponding port latch, regardles s of th e crossbar settings. the crossbar assigns the selected internal digital resou r ces to the i/o pins based on the priority decoder ( figure 12.3 and figure 12.4 ). the registers xbr0, xbr1, and xbr2, defined in sfr definition 12.1 , sfr definition 12.2 , and sfr definition 12.3 are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 12.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port0 output mode register (p0mdout). complete electrical s p ecifications for port i/o are given in table 12.1 on page 110 . xbr0, xbr1, xbr2 registers digital crossbar priority decoder sysclk 2 2 (internal digital signals) highest priority lowest priority p0 i/o cells p0.0 p0.7 8 p0mdout, p0mdin registers smbus uart t0, t1 2 4 pca p0 port latch (p0.0-p0.7) 8 cp0 outputs 2 figure 12.1. port i/o fun ctional block diagram figure 12.2. port i/o cell block diagram
c8051f300/1/2/3/4/5 104 rev. 2.9 12.1. priority crossbar decoder the priority crossb ar decoder (figure 12.3) assigns a priority to each i/o function , starting at the top with uart0. when a digital resource is selected, the least sign ificant unassigned port pin is assigned to that resource (excluding uart0, which is a lways at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next se lected resource. additionally, the crossbar will skip port pins whose associated bits in the xbr0 register are set. the xbr0 regi ster allows software to skip port pins that are to be used for analog input or gpio. important note on crossbar configuration: i f a port pin is claimed by a peripheral without use of the crossbar, its corresponding xbr0 bit should be set. this applies to p0.0 if vref is enabled, p0.3 and/or p0.2 if the external oscillator circuit is enabled, p0.6 if the adc is config ured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. figure 12.3 shows the crossbar decoder priority with no port pins skipped (xbr0 = 0x00); figure 12.4 shows the crossbar decoder prior - ity with pins 6 and 2 skipped (xbr0 = 0x44). figure 12.3. crossbar priority decoder with xbr0 = 0x00 v ref x1 x2 cnvstr 01234567 00000000 cex2 cp0a sysclk cex0 cex1 signals unavailable sf signal s pin i/o tx0 rx0 sda scl p0 cp0 port pin potentially available to peripheral sf signals eci t0 t1 xbr0[0:7] special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. note: x1 refers to the xtal1 signal; x2 refers to the xtal2 signal.
rev. 2.9 105 c8051f300/1/2/3/4/5 figure 12.4. crossbar priority decoder with xbr0 = 0x44 registers xbr1 and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assi gns both pins associated with the smbus (sda and scl). either or both of the uart signals may be selected by the crossbar. uart0 pin assignments are fixed for bootloading purposes: when uart tx0 is sele cted, it is always assigned to p0.4; when uart rx0 is selected, it is always assig ned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. for example, if assigned functions that take the first 3 port i/o (p0.[2:0]), 5 port i/o are left for analog or gpio use. v ref x1 x2 cnvstr 01234567 00100010 port pin potentially available to peripheral port pin skipped by crossbar signals unavailable rx0 sda scl cp0 cex0 cex1 special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. note: x1 refers to the xtal1 signal; x2 refers to the xtal2 signal. sf signals cex2 eci cp0a sysclk p0 xbr0[0:7] t0 t1 sf signal s pin i/o tx0
c8051f300/1/2/3/4/5 106 rev. 2.9 12.2. port i/o initialization port i/o initialization cons ists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port0 input mode r egister (p0mdin). step 2. select the output mode (open-drain or push -pull) for all port pins, using the port0 output mode register (p0mdout). step 3. set xbr0 to skip any pins selected as analog inputs or special functions. step 4. assign port pins to desired peripherals. step 5. enable the crossbar. all port pins must be configured as either analog or dig ital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver is disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in xbr0). port input mode is set in the p0mdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. see sfr defini - tion 12.5 for the p0mdin register details. the output driver characteristics of the i/o pins ar e defined using the port0 output mode register p0mdout (see sfr definition 12.6 ). each port output driver can be con figured as either open drain or push-pull. this selection is required even for the digi t al resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pi ns, which are configured as open- drain regardless of the p0mdout settings. when the weakpud bit in xbr2 is ?0?, a weak pull-up is enabled for all port i/o co nfigured as open-drain. weakpud does not affect the push-pull port i/o. fur - thermore, the weak pull-up is turned off on an open-drain output that is driving a ?0? to avoid unnecessary power dis sipation. registers xbr0, xbr1 and xbr2 must be loa ded with the appropriate values to select the digital i/o func - tions required by the design. setting the xbare bit in xbr2 to ?1? enables the crossbar. until the crossbar is enabled, the external pins remain as standard di gital inputs (output drivers disabled) regardless of the xbrn register settings. for given xbrn register setti ngs, one can determine the i/o pin-out using the priority decode table; as an altern ative, the configuration wizard utility of the silicon labs ide software will determine the port i/o pin assignments based on the xbrn register settings.
rev. 2.9 107 c8051f300/1/2/3/4/5 sfr definition 12.1. xbr0: port i/o cro ssb ar register 0 sfr definition 12.2. xbr1: port i/o crossbar register 1 bit7: unused. read = 0b; write = don?t care. bits6?0: xskp[6:0]: crossbar skip enable bits these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? xskp6 xskp5 xskp4 xskp3 xskp2 xskp1 xskp0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe1 bits7?6: pca0me: pca module i/0 enable bits 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. bit5: cp0aoen: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. bit4: cp0oen: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit3: syscke: /sysclk output enable 0: /sysclk unavailable at port pin. 1: /sysclk output routed to port pin. bit2: smb0oen: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: sda, scl routed to port pins. bit1: urx0en: uart rx enable 0: uart rx0 unavailable at port pin. 1: uart rx0 routed to port pin p0.5. bit0: utx0en: uart tx output enable 0: uart tx0 unavailable at port pin. 1: uart tx0 routed to port pin p0.4. r/w r/w r/w r/w r/w r/w r/w r/w reset value pca0me cp0aoen cp0oen syscke smb0oen urx0en utx0en 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2
c8051f300/1/2/3/4/5 108 rev. 2.9 sfr definition 12.3. xbr2: port i/o cros sbar register 2 12.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. port0 is accessed through a corr esponding special function register (sfr) that is both byte addressable and bit addressable. when writi ng to a port, the value written to the sfr is latched to maintain the output data value at each pin. when re ading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corres ponding port i/o pin). the exception to this is the execution of the read-modify-write instructions. the read-modify-write instructions when operating on a port sfr are the following: anl, orl, xrl, jbc, cp l, inc, dec, djnz and mov, clr or set, when the destination is an individual bit in a po rt sfr. for these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr. bit7: weakpud: port i/o weak pull-up disable. 0: weak pull-ups enabled (except for ports whose i/o are configured as push-pull). 1: weak pull-ups disabled. bit6: xbare: crossbar enable. 0: crossbar disabled. 1: crossbar enabled. bits5?3: unused: read = 000b. write = don?t care. bit2: t1e: t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit1: t0e: t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit0: ecie: pca0 c ounter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare ? ? ? t1e t0e ecie 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
rev. 2.9 109 c8051f300/1/2/3/4/5 sfr definition 12.4. p0: port0 register sfr definition 12.5. p0mdin: port0 input mode bits7?0: p0.[7:0] write - output appears on i/o pins per xbr0, xbr1, and xbr2 registers 0: logic low output. 1: logic high output (open-drain if corresponding p0mdout.n bit = 0) read - always reads ?1? if selected as analog input in register p0mdin. directly reads port pin when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x80 bits7?0: input configuration bits for p0.7-p0.0 (respectively) port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is co nfigured as an analog input. 1: corresponding p0.n pin is configured as a digital input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf1
c8051f300/1/2/3/4/5 110 rev. 2.9 sfr definition 12.6. p0mdout: port0 output mode table 12.1. port i/o dc electri cal characteristics v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 v dd -0.8 ?v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage 2.0 ? ? v input low voltage ? ? 0.8 v input leakage current weak pull-up off weak pull-up on, v in = 0 v ? 25 1 40 a bits7?0: output configuration bits for p0.7?p0.0 (res pectively): ignored if corresponding bit in regis- ter p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. (note: when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4
rev. 2.9 111 c8051f300/1/2/3/4/5 13. smbus the smbus i/o interface is a two-wire bidirectional se rial bus. the smbus is co mpliant with the system management bus specification, versio n 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferred at up to 1/20 th of the system clock operating as master or slave (this can be faster than allowed by the smbus spec ification, depending on the system clock used). a method of extending the clock-low duration is available to accommodate devices with differ - ent speed capabilitie s on the same bus. the smbus interface may operate as a master and/or sla v e, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl ( s erial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. three sfrs are associated with the smbus: smb0cf configures the sm bus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e b a u d 1 b a u d 0 0 1 2 3 4 5 6 7 smb0dat sda filter n figure 13.1. smbus block diagram
c8051f300/1/2/3/4/5 112 rev. 2.9 13.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), ph ilips semiconductor. 2. the i 2 c-bus specification ? versio n 2.0, philips semiconductor. 3. system management bus s pecification ? v ersion 1. 1, sbs implementers forum. 13.2. smbus configuration figure 13.2 shows a typical smbus configuration. the sm bus sp ecification allows any recessive voltage between 3.0 and 5.0 v; different devices on the bus may operate at different voltage levels. the bidirec - tional scl (serial clock) and sda (serial data) lines mu st b e connected to a positive power supply voltage through a pull-up resistor or similar circuit. every devic e connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl figure 13.2. typical smbus configuration 13.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system; any device that transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond itio n followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more byte s of data, and a stop condition. each byte that is received (by a master or slave) must be acknow ledged (ack) with a low sda during a high scl (see figure 13.3 ). if the receiving device does not ac k, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl.
rev. 2.9 113 c8051f300/1/2/3/4/5 the direction bit (r/w) occupies the least significant bi t position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the ma ste r generates the start condition and then transmits the slave address and direction bit. if the trans - action is a write operation from the ma ster to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 13.3 illustrates a typical smbus transaction. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop figure 13.3. smbus transaction 13.3.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?13.3.4. scl high (smbus free) timeout? on page 114 ). in the event that two or mo r e devices attempt to begin a transfer at the same time, an arbi - tration scheme is employed to force one master to gi ve up the bus. the master devices continue transmit - ting until one attempts a high wh ile the other transmit s a low. since the bus is open-drain, the bus will be pulled low. the master attemp ting the high will detect a low sda and lose the arbitration. the win - ning master continues its transmission without inte rr up tion; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destructive: one device always wins, and no data is lost.
c8051f300/1/2/3/4/5 114 rev. 2.9 13.3.2. clock low extension smbus provides a clock synchron ization mechanism, similar to i 2 c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 13.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 2 is used to detect scl low timeouts. timer 2 is forced to r eload when scl is high, and allowed to count when scl is low. with timer 2 enabled and configured to overflow after 25 ms (and smbtoe set), the timer 2 interrupt service routine can be used to reset (disable a nd reenable) the smbus in the event of an scl low ti meout. timer 2 configuratio n details can be found in section ?15.2. timer 2? on page 151 . 13.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is des ignated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master start, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation.
rev. 2.9 115 c8051f300/1/2/3/4/5 13.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rm ined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave ad dress that is transf erred. when transmitting, this interrupt is generated after the ack cycle so th at software may read the received ack value; when receiving data, this interrupt is generated before t he ack cycle so that software may define the outgoing ack value. see section ?13.5. smbus transfer modes? on page 123 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section ?13.4.2. smb0cn control register? on page 119 ; table 13.4 provides a quick smb0cn decoding refer - ence. smbus configuration options include: ? timeout detection (scl low timeout and/or bus free timeout) ? sda setup and hold time extensions ? slave event enable/disable ? clock source selection these options are selected in the smb0cf register, as described in se ction ?13.4.1. smbus configura - tion register? on page 116 .
c8051f300/1/2/3/4/5 116 rev. 2.9 13.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). table 13.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow the smbcs1-0 bits select the smbus clo ck source, which is used on ly when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 13.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?15. timers? on page 143 . t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == equation 13.1. minimum scl high and low ti mes the selected clock source should be configured to establish the minimum scl high and low times as per equation 13.1 . when the interface is operating as a master ( a nd scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is app ro ximated by equation 13.2 . bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = equation 13.2. typical smbus bit rate figure 13.4 shows the typical scl generation described by equation 13.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exce ed the limits defined by equation equation 13.1 .
scl timer source overflows scl high timeout t low t high rev. 2.9 117 c8051f300/1/2/3/4/5 figure 13.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 13.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mh z. table 13.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks *note: setup time for ack bit transmissions and the msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same wr ite that defines the ou tgoing ack value, s/w delay is zero. with the smbtoe bit set, timer 2 should be configured to overflow after 25 ms in order to detect scl low timeout s (see section ?13.3.3. scl low timeout? on page 114 ). the smbus interf ace will force t i mer 2 to reload while scl is high, and allow timer 2 to count wh en scl is low. the timer 2 interrupt service rou - tine should be used to reset smbus communication by disabling and reenabling the smbus. timer 2 con - figuration is described in section ?15.2. timer 2? on page 151 . smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is s e t, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 13.4 ). when a free timeout is dete cted, the interface will res p ond as if a stop was detected (an interrupt will be generat ed, and st o will be set).
c8051f300/1/2/3/4/5 118 rev. 2.9 sfr definition 13.1. smb0cf: smbus clock/configuration bit7: ensmb: smbus enable. this bit enables/disables the smbus interface. when enabled, the interface constantly mon- itors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit6: inh: smbus slave inhibit. when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit5: busy: smbus busy indicator. this bit is set to logic 1 by hardware when a tran sfer is in progress. it is cleared to logic 0 when a stop or free timeout is sensed. bit4: exthold: smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 13.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit3: smbtoe: smbus scl ti meout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 2 to reload while scl is high and allows timer 2 to count when scl goes low. if timer 2 is con- figured in split mode (t2split is set), only the high byte of ti mer 2 is held in reload while scl is high. timer 2 should be programmed to generate interrupts at 25 ms, and the timer 2 interrupt service routine should reset smbus communication. bit2: smbfte: smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus cl ock source periods. bits1?0: smbcs1-smbcs0: smbu s clock source selection. these two bits select the smbus clock source , which is used to generate the smbus bit rate. the selected device should be configured according to equation 13.1. r/w r/w r r/w r/w r/w r/w r/w reset value ensmb inh busy exthold smbtoe smbfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1 smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
rev. 2.9 119 c8051f300/1/2/3/4/5 13.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 13.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to servic e routines. master and txmode indi cate the master/slave state and transmit/receive modes, respectively. the sta bit indicates that a start has been detected or generated since the last smbus interrupt. when set to ?1?, the st a bit will cause the smbus to ente r master mode and generate a start when the bus becomes free. sta is not cleared by hardware after th e start is generated; it must be cleared by soft - ware. as a master, writing the sto bit will cause the hardware to generate a stop cond ition and end the current transfer after the next ack cycle. sto is cleared by hardware after the stop condition is generated. as a slave, sto indicates that a stop condition has been de tected since the last smbus interrupt. sto is also used in slave mode to manage the transition from slave receiver to slave transmitter; see section 13.5.4 for details on this procedure. if sto and sta are both set to ?1? (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if so ftware does not write the ack bit before clearing si. sda will reflec t the defined ack value immediately following a write to the ack bit; however scl will remain low un til si is cleared. if a received slave address is not acknowledged, further slave events will be ignored unt il the next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 13.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. ta b l e 13.3 lists all sources for hardware changes to the smb0cn bits. refer to table 13.4 for smbus sta - tus decoding using the smb0cn register.
c8051f300/1/2/3/4/5 120 rev. 2.9 sfr definition 13.2. bit7: master: smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit6: txmode: smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit5: sta: smbus start flag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a stop is received or a free timeout is detected). if sta is set by software as an active mast er, a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit4: sto: smbus stop flag. write: as a master, setting this bit to ?1? causes a st op condition to be transmitted after the next ack cycle. sto is cleared to ?0? by hardware when the st op is generated. as a slave, software manages this bit when sw itching from slave receiver to slave trans- mitter mode. see section 13.5.4 for details. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit3: ackrq: smbus acknowledge request. this read-only bit is set to logic 1 when the smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit2: arblost: smbus arbitration lost indicator. this read-only bit is set to logic 1 when the smbus loses arbitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit1: ack: smbus acknowledge flag. this bit defines the outgoing ack level and records incoming ack levels. it should be writ- ten each time a byte is rece ived (when ackrq=1), or read after each byte is transmitted. 0: a "not acknowledge" has been received (if in transmitter mode) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been re ceived (if in transmitter mode) or will be transmitted (if in receiver mode). bit0: si: smbus interrupt flag. this bit is set by hardware under the conditions listed in table 13.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. r r r/w r/w r r r/w r/w reset value master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc0 smb0cn: smbus control
table 13.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? ar bitration is lost. txm ode ? st art is generated. ? th e smbus interface enters transmitter mode ( after smb0dat is written before the start of an smbus frame). ? a st art is detected. ? ar bitration is lost. ? smb 0dat is not written before the st art of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. st o ? a stop is detected while addressed as a slave. ? ar bitration is lost due to a detected stop. ? a pe nding stop is generated. ackrq ? a byte ha s been received and an ack r esponse value is needed. ? after each ack cycle. arb lost ? a repeated start is detected as a master when st a is low (unwanted repeated start). ? scl is sensed low while attempting to gener - at e a stop or repeated start condition. ? s da is sensed low while transmit ting a ?1? (excluding ack bits). ? each time si is clea re d. ack ? the incoming ack value is low (acknowl - edge). ? the incoming ack value is high (not acknow ledge). si ? a start has been generated. ? l ost arbitration. ? a byte ha s been transmitted and an ack/nack received. ? a byte ha s been received. ? a st art or repeated start followed by a slave ad dress + r/w has been received. ? a stop has been received. ? m ust be cleared by software. rev. 2.9 121 c8051f300/1/2/3/4/5
c8051f300/1/2/3/4/5 122 rev. 2.9 13.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. af ter a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave r e ceiver is made with the correct data or address in smb0dat. sfr definition 13.3. bits7?0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial inter- face or a byte that has just been received on the smbus serial interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb 0cn.0) is set to logic one. the serial data in the register remains stabl e as long as the si flag is set. when the si flag is not set, the system may be in the proc ess of shifting data in/out and the cpu should not attempt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2 smb0dat: smbus data
rev. 2.9 123 c8051f300/1/2/3/4/5 13.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the interr upt is generated before the ack cycle when operating as a receiver, and after the ack cycle when operating as a transmitter. 13.5.1. master transmitter mode serial data is transmitted on sda while the serial cl ock is output on scl. the smbus interface generates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 0 (write). the master then transmits one or more bytes of serial data. after each byte is transmitted, an acknowled ge bit is generated by the slave. the transfer is en ded when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written follo wing a master transmitter interrupt. figure 13.5 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur af te r the ack cycle in this mode. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 13.5. typical mast er transmitter sequence
c8051f300/1/2/3/4/5 124 rev. 2.9 13.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direc - tion bit. in this case the data direction bit (r/w) will be logic 1 (read). serial dat a is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to ?1? and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the outgoing ackno wledge value (note: writing a ?1? to the ack bit gen - erates an ack; writing a ?0? genera tes a nack). sof t ware should write a ?0? to the ack bit after the last byte is received, to transmit a na ck. the interface exits master receiver mode after the sto bit is set and a stop is generated. note that the interface will switch to master tr ansmitter mode if smb0dat is written while an active master receiver. figure 13.6 shows a typical master rece iv er sequence. two received data bytes are shown, though any number of bytes may be r eceived. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 13.6. typical m aster receiver sequence
rev. 2.9 125 c8051f300/1/2/3/4/5 13.5.3. slave receiver mode serial data is received on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the rece ived slave address is ignored, slav e interrupts will be inhibited until the next start is detected. if the received slave addr ess is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0da t is written while an ac tive slave receiver; see section 13.5.4 for details on this procedure. figure 13.7 shows a typical slave receiver sequence. two received data bytes are shown, though any number of bytes may be received. notice that th e ?d ata byte transferred? interrupts occur before the ack cycle in this mode. p w sla s data byte data byte a a a s = start p = stop a = ack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 13.7. typical sl ave receiver sequence
c8051f300/1/2/3/4/5 126 rev. 2.9 13.5.4. slave transmitter mode serial data is transmitted on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to re ceive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. software responds to the received slave address with an ack, or ignores the received slav e address with a nack. if the received address is ignored, slave interrupts will be inhibi ted until the next start is detected. if the received sl ave address is acknowledged, software should write data to smb0dat to force the smbus into slave transmitter mode. the switch from slave receiver to slave transmitte r requires software management. software should per - form the steps outlined below only when a valid slave ad dr ess is received (indicated by the label ?rx-to-tx steps? in figure 13.8 ). step 1. set ack to ?1?. s t ep 2. write outgoing data to smb0dat. step 3. check smb0dat.7; if ?1?, do not perform steps 4, 6 or 7. step 4. set sto to ?1?. step 5. clear si to ?0?. step 6. poll for txmode => ?1?. step 7. clear sto to ?0? (must be done before the next ack cycle). the interface enters slave transmitter mode and transm it s o ne or more bytes of data (the above steps are only required before the first byte of the transfer). af ter each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, sm b0dat should be written with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be generated if smb0da t is written following a received nack while in slave transmitter mode). the interface exits slave tr ansmitter mode after receiving a stop. note that the interface will switch to slave receiver mode if smb0dat is no t written following a slave transmitter interrupt. figure 13.8 shows a typical slave transmitter sequence. tw o tr ansmitted data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur af te r the ack cycle in this mode. p r sla s data byte data byte a n a s = start p = stop n = nack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt perform rx-to-tx steps here figure 13.8. typical sl ave transmitter sequence
rev. 2.9 127 c8051f300/1/2/3/4/5 13.6. smbus status decoding the current smbus status can be easily decoded using the smb0cn register. in the table below, status vector refers to the four upper bits of smb0cn : master, txmode, sta, and sto. note that the shown response options are only the typical response s; application-specific pr ocedures are allowed as long as they conform with the smbus specification. highlighted response s are allowed but do not conform to the smbus specification. table 13.4. smbus status decoding mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0da t. 00x 1100 0 0 0 a master data or address byte was transmitted; nack received. set sta to restart transfer. 10x abort transfer. 01x 0 0 1 a master data or address byte was transmitted; ack received. load next data byte into smb0da t 00x end transfer with stop 01x end transfer with stop and st art another transfer. 11x send repeated start 10x switch to master receiver mode (clear si without writ - ing new data to smb0dat). 00x
c8051f300/1/2/3/4/5 128 rev. 2.9 master receiver 1000 1 0 x a master data byte was received; ack r equested. acknowledge received byte; read smb0da t. 001 send nack to indicate last byte , and send stop. 010 send nack to indicate last by te, and send stop fol - lowed by start. 110 send ack followed by re peated start. 101 send nack to indicate last byte , and send repeated start. 100 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0 slave transmitter 0100 0 0 0 a slave byte was transmitted; na ck received. no action required (expect - ing stop condition). 00x 0 0 1 a slave byte was transmitted; ack received. load smb0dat with next dat a byte to transmit. 00x 0 1 x a slave byte was transmitted; er ror detected. no action required (expect - ing master to end transfer). 00x 0101 0 x x an illegal stop or bus error was de tected while a slave transmis - sion was in progress. clear sto. 00x table 13.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
rev. 2.9 129 c8051f300/1/2/3/4/5 slave receiver 0010 1 0 x a slave address was received; ack r equested. acknowledge received add ress (received slave address match, r/w bit = read). 001 do not acknowledge re ceived address. 000 acknowledge received addres s, and switch to trans - mitter mode (received slave addres s match, r/w bit = write); see section 13.5.4 for procedure. 001 1 1 x lost arbitration as master; slave ad dress received; ack requested. acknowledge received add ress (received slave address match, r/w bit = read). 001 do not acknowledge re ceived address. 000 acknowledge received addres s, and switch to trans - mitter mode (received slave addres s match, r/w bit = write); see section 13.5.4 for procedure. 001 reschedule failed transfer; do not acknowledge received address 100 0010 0 1 x lost arbitration while attempting a re peated start. abort failed transfer. 00x reschedule failed transfer. 10x 0001 1 1 x lost arbitration while attempting a st op. no action required (transfer co mplete/aborted). 000 0 0 x a stop was detected while ad dressed as a slave transmitter or slave receiver. clear sto. 00x 0 1 x lost arbitration due to a detected st op. abort transfer. 00x reschedule failed transfer. 10x 0000 1 0 x a slave byte was received; ack re quested. acknowledge received byte; read smb0da t. 001 do not acknowledge rec eived byte. 000 11 x lost arbitration while transmitting a da ta byte as master. abort failed transfer. 000 reschedule failed transfer. 1 0 0 table 13.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
c8051f300/1/2/3/4/5 130 rev. 2.9 n otes :
rev. 2.9 131 c8051f300/1/2/3/4/5 14. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?14.1. enhanced baud rate generation? on page 132 ). received data buf f ering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous dat a byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. reading sbuf0 accesses the buffered receive re gister; writing sbuf0 access es the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0) , or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). uart baud rate generator ri scon0 ri0 ti0 rb80 tb80 ren0 mce0 s0mode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf0 read sbuf sfr bus crossbar rx sbuf (rx latch) figure 14.1. uart0 block diagram
c8051f300/1/2/3/4/5 132 rev. 2.9 14.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 14.2 ), which is not user accessible. both tx and rx timer overflows are divid ed b y two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de t e cted on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart0 figure 14.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see sect ion ?15.1.3. mode 2: 8-bit coun - ter/timer with auto-reload? on page 145 ). the timer 1 reload value should be se t s o that overflows will occur at two times the desired uart baud rate frequency. note that timer 1 may be clocked by one of five sources: sy sclk, sysclk / 4, sys clk / 12, sysclk / 48, or the external oscillator clock / 8. for any giv e n timer 1 clock source, the uart0 baud rate is determined by equation 14.1 . uartbaudrate t 1 clk 256 t 1 h ? ?? ------------------------------ - 1 2 -- - ? = equation 14.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the hig h byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?15.2. timer 2? on page 151 . a quick reference for typical baud rates and system clock frequencies is given in tables 14.1 through 14.6. note that the internal osc illator may still generate the system clock when the external os cillator is driving timer 1 (see section ?15.1. timer 0 and timer 1? on page 143 for more details).
rev. 2.9 133 c8051f300/1/2/3/4/5 14.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx figure 14.3. uart interconnect diagram 14.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx pin and received at the rx pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en s o ftware writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion ( t he beginning of the stop-bit time). data recep - tion can begin any time after the ren0 receive enable bi t ( scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbu f0 r e ceive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space figure 14.4. 8-bit u art timing diagram
c8051f300/1/2/3/4/5 134 rev. 2.9 14.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit dat a bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit g oes into rb80 (scon0 .2) and the stop bit is ignored. data transmission begins when an instruction writes a d a ta byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive en able bit (scon0.4) is set to ?1?. after the stop bit is received, the data byte will be lo aded into the sbuf0 receive register if the followin g conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 figure 14.5. 9-bit u art timing diagram
rev. 2.9 135 c8051f300/1/2/3/4/5 14.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon.5) of a slave processor co nfigur es its uart such that when a stop bit is received, the uart will generate an in terrupt only if the ninth bit is logic one (rb80 = 1) signifying an address byte has been rece ived. in the uart interrupt handler, software will compare the received address with the slave's own assign ed 8-bit address. if the addresses match, the slave will clear its mce0 bit to enable interrupts on the reception of the followi ng data byte(s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce0 bit to ignore all transmissions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /o r a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). master device slave device tx rx rx tx slave device rx tx slave device rx tx +5v figure 14.6. uart multi-processor mode interconnect diagram
c8051f300/1/2/3/4/5 136 rev. 2.9 sfr definition 14.1. bit7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: mode 0: 8-bit uart with variable baud rate 1: mode 1: 9-bit uart with variable baud rate bit6: unused. read = 1b . write = don?t care. bit5: mce0: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic 1. bit4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software bit0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enab led, setting this bit to ?1? causes the cpu to vector to the uart0 interrup t service routine. this bit must be cleared manually by soft- ware. r/w r/w r/w r/w r/w r/w r/w r/w reset value s0mode ? mce0 ren0 tb80 rb80 ti0 ri0 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x98 scon0: serial port 0 control
rev. 2.9 137 c8051f300/1/2/3/4/5 sfr definition 14.2. bits7?0: sbuf0[7:0]: serial data buffer bits 7?0 (msb-lsb) this sfr accesses two registers; a transmit shif t register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is he ld for serial transmis- sion. writing a byte to sbuf0 is what initiate s the transmission. a read of sbuf0 returns the contents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99 sbuf0: serial (uart0 ) port data buffer
table 14.1. timer settings for standard ba ud rates using th e internal 24.5 mhz oscilla tor frequency: 24.5 mhz sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 2 1 0x96 57600 0.15% 426 sysclk xx 2 1 0x2b 28800 ?0.32% 848 sysclk / 4 01 0 0x96 14400 0.15% 1704 sysclk / 12 00 0 0xb9 9600 ?0.32% 2544 sysclk / 12 00 0 0x96 2400 ?0.32% 10176 sysclk / 48 10 0 0x96 1200 0.15% 20448 sysclk / 48 10 0 0x2b notes: 1. sca1-sca0 and t1m bit definitions can be found in section 15.1 . 2. x = don?t care. table 14.2. timer settings for standard baud rates using an external 25 mhz oscilla tor frequency: 25.0 mhz sysclk from external osc. 230400 ?0.47% 108 sysclk xx 2 1 0xca 115200 0.45% 218 sysclk xx 2 1 0x93 57600 ?0.01% 434 sysclk xx 2 1 0x27 28800 0.45% 872 sysclk / 4 01 0 0x93 14400 ?0.01% 1736 sysclk / 4 01 0 0x27 9600 0.15% 2608 extclk / 8 11 0 0x5d 2400 0.45% 10464 sysclk / 48 10 0 0x93 1200 ?0.01% 20832 sysclk / 48 10 0 0x27 sysclk from internal osc. 57600 ?0.47% 432 extclk / 8 11 0 0xe5 28800 ?0.47% 864 extclk / 8 11 0 0xca 14400 0.45% 1744 extclk / 8 11 0 0x93 9600 0.15% 2608 extclk / 8 11 0 0x5d notes: 1. sca1? sca0 and t1m bit definitions can be found in section 15.1 . 2. x = don?t care c8051f300/1/2/3/4/5 138 rev. 2.9 target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex)
table 14.3. timer settings for standard baud rates using an external 22.1184 mh z oscilla tor frequency: 22.1184 mhz sysclk from external osc. sysclk from internal osc. notes: 1. sca1?sca0 and t1m bit definitions can be found in section 15.1 . 2. x = don?t care. rev. 2.9 139 c8051f300/1/2/3/4/5 target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 96 sysclk xx 2 1 0xd0 115200 0.00% 192 sysclk xx 2 10xa0 57600 0.00% 384 sysclk xx 2 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysclk / 48 10 0 0x40 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70
table 14.4. timer settings for standard baud rates using an external 18.432 mhz oscilla tor frequency: 18.432 mhz sysclk from external osc. sysclk from internal osc. notes: 1. sca1?sca0 and t1m bit defin itions can be found in section 15.1 . 2. x = don?t care c8051f300/1/2/3/4/5 140 rev. 2.9 target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 80 sysclk xx 2 10xd8 115200 0.00% 160 sysclk xx 2 1 0xb0 57600 0.00% 320 sysclk xx 2 10x60 28800 0.00% 640 sysclk / 4 01 0 0xb0 14400 0.00% 1280 sysclk / 4 01 0 0x60 9600 0.00% 1920 sysclk / 12 00 0 0xb0 2400 0.00% 7680 sysclk / 48 10 0 0xb0 1200 0.00% 15360 sysclk / 48 10 0 0x60 230400 0.00% 80 extclk / 8 11 0 0xfb 115200 0.00% 160 extclk / 8 11 0 0xf6 57600 0.00% 320 extclk / 8 11 0 0xec 28800 0.00% 640 extclk / 8 11 0 0xd8 14400 0.00% 1280 extclk / 8 11 0 0xb0 9600 0.00% 1920 extclk / 8 11 0 0x88
table 14.5. timer settings for standard baud rates using an external 11 .0592 mhz oscilla tor frequency: 11.0592 mhz sysclk from external osc. 230400 0.00% 48 sysclk xx 2 1 0xe8 115200 0.00% 96 sysclk xx 2 1 0xd0 57600 0.00% 192 sysclk xx 2 1 0xa0 28800 0.00% 384 sysclk xx 2 1 0x40 14400 0.00% 768 sysclk / 12 00 0 0xe0 9600 0.00% 1152 sysclk / 12 00 0 0xd0 2400 0.00% 4608 sysclk / 12 00 0 0x40 1200 0.00% 9216 sysclk / 48 10 0 0xa0 sysclk from internal osc. 230400 0.00% 48 extclk / 8 11 0 0xfd 115200 0.00% 96 extclk / 8 11 0 0xfa 57600 0.00% 192 extclk / 8 11 0 0xf4 28800 0.00% 384 extclk / 8 11 0 0xe8 14400 0.00% 768 extclk / 8 11 0 0xd0 9600 0.00% 1152 extclk / 8 11 0 0xb8 notes: 1. sca1?sca0 and t1m bit definitions can be found in section 15.1 . 2. x = don?t care rev. 2.9 141 c8051f300/1/2/3/4/5 target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex)
table 14.6. timer settings for standard baud rates using an external 3.6864 mhz oscilla tor frequency: 3.6864 mhz sysclk from external osc. 230400 0.00% 16 sysclk xx 2 1 0xf8 115200 0.00% 32 sysclk xx 2 1 0xf0 57600 0.00% 64 sysclk xx 2 1 0xe0 28800 0.00% 128 sysclk xx 2 1 0xc0 14400 0.00% 256 sysclk xx 2 1 0x80 9600 0.00% 384 sysclk xx 2 1 0x40 2400 0.00% 1536 sysclk / 12 00 0 0xc0 1200 0.00% 3072 sysclk / 12 00 0 0x80 sysclk from internal osc. 230400 0.00% 16 extclk / 8 11 0 0xff 115200 0.00% 32 extclk / 8 11 0 0xfe 57600 0.00% 64 extclk / 8 11 0 0xfc 28800 0.00% 128 extclk / 8 11 0 0xf8 14400 0.00% 256 extclk / 8 11 0 0xf0 9600 0.00% 384 extclk / 8 11 0 0xe8 notes: 1. sca1?sca0 and t1m bit definitions can be found in section 15.1 . 2. x = don?t care c8051f300/1/2/3/4/5 142 rev. 2.9 target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex)
rev. 2.9 143 c8051f300/1/2/3/4/5 15. timers each mcu includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time inte rvals, count external even ts and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. ti m er 2 offers 16-bit and split 8-bit timer functionality with auto-reload. timer 0 and timer 1 modes: timer 2 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only) timers 0 and 1 may be clocked by one of five so u r ces, determined by the timer mode select bits (t1m?t0m) and the clock scale bits (sca1?sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 15.3 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sc aled clock s i gnal or the system clock. timer 2 may be clocked by the sys tem clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when fun c tioning as a counter, a counter/timer register is incremented on each high -to-low transition at the selected input pin. events with a frequency of up to one-fourth the system clock's frequency can be counted. th e input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sam - pled. 15.1. timer 0 and timer 1 each timer is implemented as 16-bit register accessed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate their status. timer 0 interrupts can be enabled by setting the et0 bit in the ie register ( section ?8.3.5. interrupt register descriptions? on page 75 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( section 8.3.5 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1?t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 15.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operat e identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c oun te r/timer. tl0 holds the five lsbs in bit positions tl0.4-tl0.0. the three upper bits of tl0 (tl0.7-tl0 .5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf 0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled.
c8051f300/1/2/3/4/5 144 rev. 2.9 the c/t0 bit (tmod.2) selects the counter/timer's cloc k source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?12.1. priority crossbar decoder? on page 104 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 15.3 ). setting the tr0 bit (tcon.4) enables the timer when ei th er gate0 (tmod.3) is logic 0 or the input signal /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 8.11 ). setting gate0 to ?1? allows the timer to be controlled by the external input signal /int0 (see section ?8.3.5. interrupt register descriptions? on page 75 ), facilitating pulse wid th measurement s. tr0 gate0 /int0 counter/timer *note: x = don't care setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1; the /int1 polari ty is defined by bit in1pl in register it01cf (see sfr definition 8.11 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor figure 15.1. t0 mode 0 block diagram 0 x* x* disabled 10x*enabled 1 1 0 disabled 111enabled
rev. 2.9 145 c8051f300/1/2/3/4/5 15.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun - ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 15.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enable d, an interrupt will occur when the tf0 flag is set. the reload va lue in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal /int0 is active as defined by bit in0pl in register it01cf (see section ?8.3.2. external interrupts? on page 73 for details on the external input signals /int0 and /int1). tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar figure 15.2. t0 mode 2 block diagram
c8051f300/1/2/3/4/5 146 rev. 2.9 15.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun - ter/timer in tl0 is controlled using the timer 0 contro l/st a tus bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 over flow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mod e 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud ra tes for the smbus and/or ua rt, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in m ode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar figure 15.3. t0 mode 3 block diagram
rev. 2.9 147 c8051f300/1/2/3/4/5 sfr definition 15.1. bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. when it1 = 0, this flag is set to ?1? when /int1 is active as defined by bit in1pl in register it01cf (see sfr definition 8.11). bit2: it1: interrupt 1 type select. this bit selects whether the co nfigured /int1 interrupt will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 8.11). 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. when it0 = 0, this flag is set to ?1? when /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 8.11). bit0: it0: interrupt 0 type select. this bit selects whether the co nfigured /int0 interrupt will be edge or level sensitive. /int0 is configured active low or high by the in0p l bit in register it01cf (see sfr definition 8.11). 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x88 tcon: timer control
c8051f300/1/2/3/4/5 148 rev. 2.9 sfr definition 15.2. bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in regis- ter it01cf (see sfr definition 8.11). bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5?4: t1m1?t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in regis- ter it01cf (see sfr definition 8.11). bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1?0: t0m1?t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto- reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto- reload 1 1 mode 3: two 8-bit counter/timers tmod: timer mode
rev. 2.9 149 c8051f300/1/2/3/4/5 sfr definition 15.3. bit7: unused. read = 0b, write = don?t care. bit6: t2mh: timer 2 high byte clock select this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8- bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit5: t2ml: timer 2 lo w byte clock select this bit selects the clock supplie d to timer 2. if timer 2 is c onfigured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit4: t1m: timer 1 clock select. this select the clock source su pplied to timer 1. t1m is ignore d when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1?sca0. 1: timer 1 uses the system clock. bit3: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1?sca0. 1: counter/timer 0 uses the system clock. bit2: unused. read = 0b, write = don?t care. bits1?0: sca1?sca0: timer 0/1 prescale bits these bits control the division of the clock su pplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? t2mh t2ml t1m t0m ? sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 note: external clock divided by 8 is synchronized with the system clock, and the exte rnal clock must be less than or equal to the system clock to operate in this mode. ckcon: clock control
c8051f300/1/2/3/4/5 150 rev. 2.9 sfr definition 15.4. bits 7?0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a tl0: timer 0 low byte sfr definition 15.5. bits 7?0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8b tl1: timer 1 low byte sfr definition 15.6. bits 7?0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8c th0: timer 0 high byte sfr definition 15.7. bits 7?0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8d th1: timer 1 high byte
rev. 2.9 151 c8051f300/1/2/3/4/5 15.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the sy stem clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 15.2.1. 16-bit timer with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is load ed into the timer 2 register as shown in figure 15.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is se t. if t imer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generat ed on each timer 2 overflow. additiona lly, if timer 2 inte rrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2l tf2h t2xclk tr2 0 1 t2xclk ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m interrupt tf2len to adc, smbus to smbus tmr2l overflow figure 15.4. timer 2 16-bi t mode block diagram
c8051f300/1/2/3/4/5 152 rev. 2.9 15.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 15.5 . tmr2rll holds the reload va lue for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr 2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sys clk , sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk note: external clock divided by 8 is synchronized with the s ystem clock, and the external clock must be less than or equal to the system clock to operate in this mode. the tf2h bit is set when tmr2h overflows from 0xff to 0x00 ; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. wh en tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus figure 15.5. timer 2 8- bit mode block diagram
rev. 2.9 153 c8051f300/1/2/3/4/5 sfr definition 15.8. tmr2cn: timer 2 control bit7: tf2h: timer 2 high byte overflow flag set by hardware when the timer 2 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xff ff to 0x0000. when the timer 2 inte rrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automatically cleared by hard ware and must be cleared by software. bit6: tf2l: timer 2 low byte overflow flag set by hardware when the timer 2 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf2len is set and timer 2 interr upts are enabled. tf2l will set when the low byte overflows regardless of the timer 2 mode. this bit is not automat- ically cleared by hardware. bit5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte in terrupts. if tf2len is set and timer 2 inter- rupts are enabled, an interrupt w ill be generated when the low byte of timer 2 overflows. this bit should be cleared when operating timer 2 in 16-bit mode. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit4: unused. read = 0b . write = don?t care. bit3: t2split: timer 2 split mode enable when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit1: unused. read = 0b . write = don?t care. bit0: t2xclk: timer 2 external clock select this bit selects the external cl ock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external o scillator clock source for both time r bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ck con) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf2h tf2l tf2len ? t2split tr2 ? t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc8
c8051f300/1/2/3/4/5 154 rev. 2.9 sfr definition 15.9. tmr2rll: timer 2 relo ad register low byte bits 7?0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca sfr definition 15.10. tmr2rlh: timer 2 relo ad register high byte bits 7?0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb sfr definition 15.11. tmr2l: timer 2 low byte bits 7?0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc sfr definition 15.12. tmr2h timer 2 high byte bits 7?0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains t he high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcd
rev. 2.9 155 c8051f300/1/2/3/4/5 16. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?12.1. priority crossbar decoder? on page 104 for details on configuring the crossbar). the counter/timer is driven by a programmable timebase that can select between six so urc e s: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflow, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre - quency output, 8-bit pwm, or 16-bit pwm (e ach mod e is described in section ?16.2. capture/compare modules? on page 157 ). the external oscillator clock option is i deal for real-time clock (rtc) functionality, allowing the pca to be clocked by a precis ion external osc ill ator while the internal oscillator drives the sys - tem clock. the pca is configured and controlled th ro ugh the system controller's special function regis - ters. the basic pca block diagram is shown in figure 16.1 . important note: t h e pca module 2 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled. see section 16.3 for details. 16-bit counter/timer cex1 eci digital crossbar cex2 cex0 port i/o capture/compare module 1 capture/compare module 0 capture/compare module 2 / wdt pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 16.1. pca block diagram
c8051f300/1/2/3/4/5 156 rev. 2.9 16.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter . reading pca0h or pca0l does not disturb the counte r operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 16.1 . note that in ?external oscillator source divided by 8? mode, the external oscillator source is synchr onized w ith the system clock, and must have a frequency less than or equal to the system clock. when the counter/timer overflows from 0xffff to 0x0 000 , the coun ter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware (note: pca0 interrupts must be globally enabled before cf interrupts are recognized. pca0 inter - rupts are globally enabled by setting the ea bit and th e epca0 bit to logic 1). cle ar ing the cidl bit in the pca0md register allows the pca to continue no rmal operation while the cpu is in idle mode. table 16.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator source divided by 8 * *note: external oscillator source divided by 8 is synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 100 101 sysclk external clock/8 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules figure 16.2. pca counter /timer block diagram
rev. 2.9 157 c8051f300/1/2/3/4/5 16.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special func tion registers (sfrs) asso ciated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 16.2 summarizes the bit settings in the pca0cpmn r egisters used to select the pca capture/com - pare module?s operating modes. setting the eccfn bi t in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec - ognized. pca0 interrupts are globally enabled by se tting the ea bit and the epca0 bit to logic 1. see figure 16.3 for details on the pca interrupt configuration. table 16.2. pca0cpm register settings fo r pca capture/compare modules pwm16 ecom capp capn mat tog pwm eccf operation mode x* x* 1 0 0 0 0 x* capture triggered by positive edge on cexn x* x* 0 1 0 0 0 x* capture triggered by negative edg e on cexn x* x* 1 1 0 0 0 x* capture triggered by transition on cexn x* 1 0 0 1 0 0 x* software timer x* 1 0 0 1 1 0 x* high speed output x* 1 0 0 x* 1 1 x* frequency output 0 1 0 0 x* 0 1 x* 8-bit pulse width modulator 1 1 0 0 x* 0 1 x* 16-bit pulse width modulator *note: x = don?t care pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/ timer overflow 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n interrupt priority decoder epca0 0 1 ea 0 1 figure 16.3. pca interrupt block diagram
note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware. c8051f300/1/2/3/4/5 158 rev. 2.9 16.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture th e value of the pca counter/ timer and copy it into the corresponding module 's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p o s itive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when th e cpu vectors to the interrupt service routine, and must be cleared by softwa re. if both cappn and capn n bits are set to logic 1, then the state of the port p i n associated with cexn can be read directly to de termine whether a rising-edge or falling-edge caused the capture. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt 0 000x x figure 16.4. pca capture mode diagram
rev. 2.9 159 c8051f300/1/2/3/4/5 16.2.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not autom atically cleared by hard ware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. figure 16.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
c8051f300/1/2/3/4/5 160 rev. 2.9 16.2.3. high speed output mode in high speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high- speed output mode. important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. figure 16.6. pca high speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
rev. 2.9 161 c8051f300/1/2/3/4/5 16.2.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 16.1 . equation 16.1. square wave fr equency output where f pca is the frequency of the clock selected by the cps2?0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg - ister. figure 16.7. pca frequency output mode f cexn f pca 2 pca0 cphn ? 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset
c8051f300/1/2/3/4/5 162 rev. 2.9 16.2.5. 8-bit pulse width modulator mode each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is depe nde nt on the timebase for the pca counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca counter/ti mer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be set to ?1?. when the count value in pc a0l overflows, the cexn output will be set to ?0? (see figure 16.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the va lue stored in the module?s capture/compare high byte (pca0cphn) without software intervention. se tting the ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode . the duty cycle for 8-bit pwm mode is given by equation 16.2 . important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. equation 16.2. 8-bit pwm duty cycle using equation 16.2, the largest duty cycle is 100% (pca0c ph n = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be g enerated by clearing the ecomn bit to ?0?. figure 16.8. pca 8-bi t pwm mode diagram dutycycle 256 pca0 cphn ? ?? 256 ----------------------------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset
rev. 2.9 163 c8051f300/1/2/3/4/5 16.2.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare mod - ule defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches th e module contents, the output on cexn is set to ?1?; when the counter overflows, cexn is set to ?0?. to output a varying duty cycle, new value writes shou ld be synchronized with pc a ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchro - nize the capture/compare register writes. the du ty cycle for 16-bit pwm mode is given by equation 16.3 . important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. equation 16.3. 16-bit pwm duty cycle using equation 16.3, the largest duty cycle is 100% (pca0c pn = 0) , and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. figure 16.9. pca 16-bit pwm mode dutycycle 65536 pca0 cpn ? ?? 65536 ---------------------------------------------------- - = pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
c8051f300/1/2/3/4/5 164 rev. 2.9 16.3. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 2. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 2 operates as a watchdog timer (wdt). the mod - ule 2 high byte is compared to the pca counter high b yte; the module 2 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. 16.3.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2?cps0) are frozen. ? pca idle control bi t ( cidl) is frozen. ? module 2 is forced in to sof tware timer mode. ? writes to the module 2 mode register (pca0cpm2) are disabled. while the wdt is enabled, writes to the cr bit will not c hange the pca counter state; the counter will run until the wdt is disabled. the pca co unter run co ntrol (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a ma tch occurs between pca0cph2 and pca0h while the wdt is enabled, a reset will be gener ated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph2. upon a pca0cph2 write, pca0h plus the offset held in pca0cpl2 is loaded into pca0cph2 (see figure 16.10 ). figure 16.10. pca module 2 wi th watchdog timer enabled pca0h enable pca0l overflow reset pca0cpl2 8-bit adder pca0cph2 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator
rev. 2.9 165 c8051f300/1/2/3/4/5 note that the 8-bit offset held in pca0cph2 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 16.4 , where pca0l is the value of the pca0l register at the time of the update. equation 16.4. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph2 and pca0h. software may force a wdt reset by writing a ?1? to the ccf2 flag (pca0cn.2) while the wdt is enabled. 16.3.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a ?0? to the wdte bit. ? select the desired pca clock s our ce (with the cps2?cps0 bits). ? load pca0cpl2 with the desi r ed wdt update offset value. ? configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to ?1?. ? reload the wdt by writing any value to pca0cph2. the pca clock source and idle mode select cannot be chan ged while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. th e pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl2 defaults to 0x00. using equation 16.4 , this results in a wdt timeout interval of 3072 system clock cycles. ta b l e 16.3 lists some example time out interv als for typical system clocks, assuming sysclk / 12 as t he pca clock source. offset 256 pca0 cpl2 ? ?? 256 pca0 l ? ?? + =
c8051f300/1/2/3/4/5 166 rev. 2.9 table 16.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl2 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 18,432,000 255 42.7 18,432,000 128 21.5 18,432,000 32 5.5 11,059,200 255 71.1 11,059,200 128 35.8 11,059,200 32 9.2 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168 notes: 1. assumes sysclk / 12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal oscillator reset frequency for devices with a calibrated internal oscillator. the reset system clock for devices with an uncalibrated internal oscillator will vary.
rev. 2.9 167 c8051f300/1/2/3/4/5 16.4. register descriptions for pca following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr definition 16.1. pca0cn: pca control bit7: cf: pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) inte rrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bi t is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca counter/ timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. bits5?3: unused. read = 000b, write = don't care. bit2: ccf2: pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf2 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit1: ccf1: pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf1 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit0: ccf0: pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when t he ccf0 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value cf cr ? ? ? ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd8
c8051f300/1/2/3/4/5 168 rev. 2.9 sfr definition 16.2. pca0md: pca mode bit7: cidl: pca counte r/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while the system controller is in idle mode. bit6: wdte: watchdog timer enable if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. bit5: wdlck: watchdog timer lock this bit locks/unlocks the watchdog timer en able. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. bit4: unused. read = 0b, write = don't care. bits3?1: cps2?cps0: pca coun ter/timer pulse select. these bits select the clock source for the pca counter bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the pca0 md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value cidl wdte wdlck ? cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external clock divided by 8 * 1 1 0 reserved 1 1 1 reserved *note: external oscillator source divided by 8 is synchronized with the system clock.
rev. 2.9 169 c8051f300/1/2/3/4/5 sfr definition 16.3. pca0cpmn: pca capture/compare mode pca0cpmn address: pca0cpm0 = 0xda (n = 0) pca0cpm1 = 0xdb (n = 1) pca0cpm2 = 0xdc (n = 2) bit7: pwm16n: 16-bit pulse width modulation enable. this bit selects 16-bit mode when pulse wi dth modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the comparator function for pca module n. 0: disabled. 1: enabled. bit5: cappn: capture positive function enable. this bit enables/disables the positive edge capture for pca module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca module n. when enabled, matches of the pca counter with a module's capture/compare regi ster cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca module n. when enabled, matches of the pca counter with a module's capture/compare regi ster cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in fre- quency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn mat n togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xda, 0xdb, 0xdc
c8051f300/1/2/3/4/5 170 rev. 2.9 sfr definition 16.4. pca0l: pca counter/timer low byte sfr definition 16.5. pca0h: pca counter/t imer high byte bits 7?0: pca0l: pca co unter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bi t2 bit1 bit0 sfr address: 0xf9 bits 7?0: pca0h: pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfa
rev. 2.9 171 c8051f300/1/2/3/4/5 sfr definition 16.6. pca0cpln: pca capture module low byte sfr definition 16.7. pca0cphn: pca captur e module high byte pca0cpln address: pca0cpl0 = 0xfb (n = 0) pca0cpl1 = 0xe9 (n = 1) pca0cpl2 = 0xeb (n = 2) bits7?0: pca0cpln: pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfb, 0xe9, 0xeb pca0cphn address: pca0cph0 = 0xfc (n = 0) pca0cph1 = 0xea (n = 1) pca0cph2 = 0xec(n = 2) bits7?0: pca0cphn: pca ca pture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfc, 0xea, 0xec
c8051f300/1/2/3/4/5 172 rev. 2.9 n otes :
rev. 2.9 173 c8051f300/1/2/3/4/5 17. c2 interface c8051f300/1/2/3/4/5 devices include an on-chip silicon labs 2-wire (c2) debug interf ace to allow flash programming and in-system debugging with the producti on part installed in the end application. the c2 interface operates using only two pi ns: a bi-directional data signal (c2d) and a clock input (c2ck). see the c2 interface specification for details on the c2 protocol. 17.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec - ification. c2 register definition 17.1. bits7?0: the c2add register is accessed via the c2 interface to select the ta rget data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id regist er for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programming data register for data read/write instructions 0x80 selects the port0 register for data read/write instructions 0xf1 selects the port0 input mode regi ster for data read/write instruc- tions 0xa4 selects the port0 output mode register for data read/write instructions c2add: c2 address c2 register definition 17.2. this read-only register returns the 8-bi t device id: 0x04 (c8051f300/1/2/3/4/5). reset value 00000100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 deviceid: c2 device id
c8051f300/1/2/3/4/5 174 rev. 2.9 c2 register definition 17.3. revid: c2 revision id this read-only register returns the 8-bit revision id: 0x00 (revision a) reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c2 register definition 17.4. fpctl: c2 flash programming control bits7?0 fpctl: flash programming control register this register is used to enable flash programmi ng via the c2 interface. to enable c2 flash programming, the following codes must be writte n in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset mu st be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c2 register definition 17.5. fpdat: c2 flash programming data bits7?0: fpdat: c2 flash programming data register this register is used to pass flash comma nds, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
rev. 2.9 175 c8051f300/1/2/3/4/5 17.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming functions may be performed. this is possible because c2 co mmunication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?borrow? the c2ck (normally rst ) and c2d (normally p0.7) pins. in most applications, external resistors are requir ed to isolate c2 interface traffic from the user appli - cation. a typical isolation config ura tion is shown in figure 17.1 . c2d (p0.7) c2ck (/rst) /reset (a) input (b) output (c) c2 interface master c8051f300 figure 17.1. typical c2 pin sharing the configuration in figure 17.1 assumes the following: 1. the user input (b) cannot change stat e while the t arget device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application.
d ocument c hange l ist revision 2.3 to revision 2.4 ? removed preliminary tag. ? changed all references of mlp package to qfn p a ckage. ? pinout chapter: figure 4.3: changed title to ?t ypical q fn-11 solder paste mask.? ? adc chapter: added re fer ence to minimum tracking time in the tracking modes section. ? comparators chapter: sfr definition 7.3, cpt0m d : updated the register reset value and the cp0 response time table. ? cip51 chapter: updated idle mode and rec - ommendations. ? cip51 chapter: updated interrupt behavior and ea re co mmendations. ? cip51 chapter: sfr definition 8.4, psw: clari - fied ov flag description. ? cip51 chapter: sfr definition 8.8, ip register: cha nge d ?default priority order? to ?low priority? for low priority descriptions. ? reset sources chapter: clarified description of vdd ramp t ime. ? reset sources chapter: t a ble 9.2, ?reset elec - trical characteristics? : adde d vdd ramp time and changed ?vdd por threshold? to ?vdd monitor threshold.? ? flash memory chapter: cla r ified descriptions of flash security features. ? oscillators chapter: ta b l e 11.1 ?internal oscil - lator electrical characteristics?: added cali - brated internal oscillato r spec i fication over a smaller temperature range. ? oscillators chapter: clarified external crystal initializ ation step s and added a specific 32.768 khz crystal example. ? oscillators chapter: clari fied external cap acitor example. ? smbus chapter: figure 14.5, smb0cf regis - ter: added a description of the behavior of t i mer 3 in split mode if smbtoe is set. ? timers chapter: changed references to ?tl2? a nd ? th2? to ?tmr2l? and ?tmr2h,? respec - tively. revision 2.4 to revision 2.5 ? fixed variables and applied formatting changes. revision 2.5 to revision 2.6 ? updated table 1.1 product selection guide to include lead-free information. revision 2.6 to revision 2.7 ? removed non-rohs compliant devices from table 1.1, ?product selection guide,? on page 14. ? added min and max specifications for adc of fset error and adc full scale error to table 5.1, ?adc0 electrical characteristics,? on page 47 . ? improved power supply s p ecifications in table 3.1, ?global electric al ch ar acteristics,? on page 25 . ? added section ?10.4. flash write and erase guidelines? on page 94 . ? fixed minor typographical errors throughout. revision 2.7 to revision 2.8 ? updated block diagram on page 1. revision 2.8 to revision 2.9 ? updated qfn package drawings and notes. ? added soic-14 package information. ? added text to cpt0cn's sfr definition to indi - cate that the sfr is bit addressable. ? changed smbus maximum transfer speed fro m 1/10th system clo ck to 1/20th system clock in smbus section. ? added information pertaining to slave receiver an d slave transmitter states in table 13.4. ? changed table 5.1 and figure 5.4 to indicate that 1 1 sar clocks are needed for a sar con - version to complete. ? changed scon0s sfr definition to show that scon0 bit 6 always r esets to a value of 1. c8051f300/1/2/3/4/5 176 rev. 2.9
rev. 2.9 177 c8051f300/1/2/3/4/5 n otes :
c8051f300/1/2/3/4/5 178 rev. 2.9 c ontact i nformation silicon laboratories inc. 4635 boston lane ? austin, tx 78735 ? tel: 1+(512) 416-8500 ? fax: 1+(512) 416-9669 ? toll free: 1+(877) 444-3032 email: mcuinfo@silabs.com ? internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assume s no responsibility for errors and omissi ons, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsi- bility for the functioning of undescribed features or parameters. si licon laboratories reserves the right to make changes with- out further notice. silicon laboratories makes no warranty, r epresentation or guarantee regarding the suitability of its produc ts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any pro d- uct or circuit, and specifically disclaims any and all liability, including wit hout limitation consequential or incidental dama ges. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where pers onal injury or death may occur. should buyer purchase or use si licon laboratories products for any such unintended or unauthor- ized application, buyer shall indemni fy and hold silicon laboratories harml ess against all claims and damages.
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